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drm/amd/pp: Change pstate_clk frequency unit to 10KHz on Rv
to keep consistent with other asics Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 2 additions and 2 deletions
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@ -479,8 +479,8 @@ static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
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hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK;
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hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK;
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hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
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hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
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return result;
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}
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