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watchdog: it87_wdt: Keep WDTCTRL bit 3 unmodified for IT8784/IT8786

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WDTCTRL bit 3 sets the mode choice for the clock input of IT8784/IT8786.
Some motherboards require this bit to be set to 1 (= PCICLK mode),
otherwise the watchdog functionality gets broken. The BIOS of those
motherboards sets WDTCTRL bit 3 already to 1.

Instead of setting all bits of WDTCTRL to 0 by writing 0x00 to it, keep
bit 3 of it unchanged for IT8784/IT8786 chips. In this way, bit 3 keeps
the status as set by the BIOS of the motherboard.

Watchdog tests have been successful with this patch with the following
systems:
  IT8784: Thomas-Krenn LES plus v2 (YANLING YL-KBRL2 V2)
  IT8786: Thomas-Krenn LES plus v3 (YANLING YL-CLU L2)
  IT8786: Thomas-Krenn LES network 6L v2 (YANLING YL-CLU6L)

Link: https://lore.kernel.org/all/140b264d-341f-465b-8715-dacfe84b3f71@roeck-us.net/

Signed-off-by: Werner Fischer <devlists@wefi.net>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20231213094525.11849-4-devlists@wefi.net
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Werner Fischer 2023-12-13 10:45:25 +01:00 committed by Wim Van Sebroeck
parent ab6dea00fd
commit d12971849d
1 changed files with 13 additions and 1 deletions
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14
drivers/watchdog/it87_wdt.c
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@ -258,6 +258,7 @@ static struct watchdog_device wdt_dev = {
static int __init it87_wdt_init(void)
{
u8 chip_rev;
u8 ctrl;
int rc;
rc = superio_enter();
@ -316,7 +317,18 @@ static int __init it87_wdt_init(void)
superio_select(GPIO);
superio_outb(WDT_TOV1, WDTCFG);
superio_outb(0x00, WDTCTRL);
switch (chip_type) {
case IT8784_ID:
case IT8786_ID:
ctrl = superio_inb(WDTCTRL);
ctrl &= 0x08;
superio_outb(ctrl, WDTCTRL);
break;
default:
superio_outb(0x00, WDTCTRL);
}
superio_exit();
if (timeout < 1 || timeout > max_units * 60) {