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clk: renesas: r8a77995: Add ZA2 clock
[ Upstream commit 790c06cc5d
]
R-Car D3 ZA2 clock is from PLL0D3 or S0,
and it can be controlled by ZA2CKCR.
It is needed for R-Car Sound, but is not used so far.
Using default settings is very enough at this point.
This patch adds it by DEF_FIXED().
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87pmxclrmy.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -73,6 +73,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
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/* Core Clock Outputs */
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DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
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DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
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DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
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DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
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