mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 17:59:32 +00:00
sparc64: Cache per-cpu %pcr register value in perf code.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
6e804251d1
commit
d17513889a
1 changed files with 42 additions and 17 deletions
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@ -56,7 +56,8 @@ struct cpu_hw_events {
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struct perf_event *events[MAX_HWEVENTS];
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struct perf_event *events[MAX_HWEVENTS];
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unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
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unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
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unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
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unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
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int enabled;
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u64 pcr;
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int enabled;
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};
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};
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
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@ -464,21 +465,30 @@ static u64 nop_for_index(int idx)
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sparc_pmu->lower_nop, idx);
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sparc_pmu->lower_nop, idx);
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}
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}
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static inline void sparc_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
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{
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{
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u64 val, mask = mask_for_index(idx);
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u64 val, mask = mask_for_index(idx);
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val = pcr_ops->read();
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val = cpuc->pcr;
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pcr_ops->write((val & ~mask) | hwc->config);
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val &= ~mask;
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val |= hwc->config;
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cpuc->pcr = val;
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pcr_ops->write(cpuc->pcr);
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}
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}
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static inline void sparc_pmu_disable_event(struct hw_perf_event *hwc, int idx)
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static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
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{
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{
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u64 mask = mask_for_index(idx);
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u64 mask = mask_for_index(idx);
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u64 nop = nop_for_index(idx);
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u64 nop = nop_for_index(idx);
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u64 val = pcr_ops->read();
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u64 val;
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pcr_ops->write((val & ~mask) | nop);
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val = cpuc->pcr;
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val &= ~mask;
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val |= nop;
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cpuc->pcr = val;
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pcr_ops->write(cpuc->pcr);
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}
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}
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void hw_perf_enable(void)
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void hw_perf_enable(void)
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@ -493,7 +503,7 @@ void hw_perf_enable(void)
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cpuc->enabled = 1;
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cpuc->enabled = 1;
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barrier();
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barrier();
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val = pcr_ops->read();
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val = cpuc->pcr;
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for (i = 0; i < MAX_HWEVENTS; i++) {
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for (i = 0; i < MAX_HWEVENTS; i++) {
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struct perf_event *cp = cpuc->events[i];
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struct perf_event *cp = cpuc->events[i];
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@ -505,7 +515,9 @@ void hw_perf_enable(void)
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val |= hwc->config_base;
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val |= hwc->config_base;
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}
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}
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pcr_ops->write(val);
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cpuc->pcr = val;
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pcr_ops->write(cpuc->pcr);
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}
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}
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void hw_perf_disable(void)
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void hw_perf_disable(void)
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@ -518,10 +530,12 @@ void hw_perf_disable(void)
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cpuc->enabled = 0;
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cpuc->enabled = 0;
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val = pcr_ops->read();
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val = cpuc->pcr;
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val &= ~(PCR_UTRACE | PCR_STRACE |
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val &= ~(PCR_UTRACE | PCR_STRACE |
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sparc_pmu->hv_bit | sparc_pmu->irq_bit);
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sparc_pmu->hv_bit | sparc_pmu->irq_bit);
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pcr_ops->write(val);
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cpuc->pcr = val;
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pcr_ops->write(cpuc->pcr);
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}
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}
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static u32 read_pmc(int idx)
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static u32 read_pmc(int idx)
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@ -593,13 +607,13 @@ static int sparc_pmu_enable(struct perf_event *event)
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if (test_and_set_bit(idx, cpuc->used_mask))
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if (test_and_set_bit(idx, cpuc->used_mask))
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return -EAGAIN;
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return -EAGAIN;
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sparc_pmu_disable_event(hwc, idx);
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sparc_pmu_disable_event(cpuc, hwc, idx);
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cpuc->events[idx] = event;
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cpuc->events[idx] = event;
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set_bit(idx, cpuc->active_mask);
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set_bit(idx, cpuc->active_mask);
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sparc_perf_event_set_period(event, hwc, idx);
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sparc_perf_event_set_period(event, hwc, idx);
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sparc_pmu_enable_event(hwc, idx);
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sparc_pmu_enable_event(cpuc, hwc, idx);
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perf_event_update_userpage(event);
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perf_event_update_userpage(event);
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return 0;
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return 0;
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}
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}
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@ -635,7 +649,7 @@ static void sparc_pmu_disable(struct perf_event *event)
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int idx = hwc->idx;
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int idx = hwc->idx;
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clear_bit(idx, cpuc->active_mask);
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clear_bit(idx, cpuc->active_mask);
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sparc_pmu_disable_event(hwc, idx);
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sparc_pmu_disable_event(cpuc, hwc, idx);
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barrier();
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barrier();
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@ -649,18 +663,29 @@ static void sparc_pmu_disable(struct perf_event *event)
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static void sparc_pmu_read(struct perf_event *event)
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static void sparc_pmu_read(struct perf_event *event)
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{
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{
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event *hwc = &event->hw;
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sparc_perf_event_update(event, hwc, hwc->idx);
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sparc_perf_event_update(event, hwc, hwc->idx);
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}
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}
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static void sparc_pmu_unthrottle(struct perf_event *event)
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static void sparc_pmu_unthrottle(struct perf_event *event)
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{
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event *hwc = &event->hw;
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sparc_pmu_enable_event(hwc, hwc->idx);
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sparc_pmu_enable_event(cpuc, hwc, hwc->idx);
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}
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}
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static atomic_t active_events = ATOMIC_INIT(0);
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static atomic_t active_events = ATOMIC_INIT(0);
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static DEFINE_MUTEX(pmc_grab_mutex);
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static DEFINE_MUTEX(pmc_grab_mutex);
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static void perf_stop_nmi_watchdog(void *unused)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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stop_nmi_watchdog(NULL);
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cpuc->pcr = pcr_ops->read();
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}
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void perf_event_grab_pmc(void)
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void perf_event_grab_pmc(void)
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{
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{
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if (atomic_inc_not_zero(&active_events))
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if (atomic_inc_not_zero(&active_events))
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@ -669,7 +694,7 @@ void perf_event_grab_pmc(void)
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mutex_lock(&pmc_grab_mutex);
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mutex_lock(&pmc_grab_mutex);
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if (atomic_read(&active_events) == 0) {
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if (atomic_read(&active_events) == 0) {
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if (atomic_read(&nmi_active) > 0) {
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if (atomic_read(&nmi_active) > 0) {
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on_each_cpu(stop_nmi_watchdog, NULL, 1);
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on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
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BUG_ON(atomic_read(&nmi_active) != 0);
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BUG_ON(atomic_read(&nmi_active) != 0);
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}
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}
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atomic_inc(&active_events);
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atomic_inc(&active_events);
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@ -978,7 +1003,7 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
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continue;
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continue;
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if (perf_event_overflow(event, 1, &data, regs))
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if (perf_event_overflow(event, 1, &data, regs))
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sparc_pmu_disable_event(hwc, idx);
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sparc_pmu_disable_event(cpuc, hwc, idx);
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}
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}
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return NOTIFY_STOP;
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return NOTIFY_STOP;
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