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usb: dwc2: add controller hibernation support
When suspending usb bus, phy driver may disable controller power. In this case, registers need to be saved on suspend and restored on resume. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Gregory Herrero
Felipe Balbi
parent
563cf017c4
commit
d17ee77b30
2 changed files with 461 additions and 0 deletions
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@ -56,6 +56,383 @@
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#include "core.h"
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#include "hcd.h"
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#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
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/**
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* dwc2_backup_host_registers() - Backup controller host registers.
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* When suspending usb bus, registers needs to be backuped
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* if controller power is disabled once suspended.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_hregs_backup *hr;
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int i;
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dev_dbg(hsotg->dev, "%s\n", __func__);
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/* Backup Host regs */
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hr = hsotg->hr_backup;
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if (!hr) {
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hr = devm_kzalloc(hsotg->dev, sizeof(*hr), GFP_KERNEL);
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if (!hr) {
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dev_err(hsotg->dev, "%s: can't allocate host regs\n",
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__func__);
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return -ENOMEM;
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}
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hsotg->hr_backup = hr;
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}
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hr->hcfg = readl(hsotg->regs + HCFG);
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hr->haintmsk = readl(hsotg->regs + HAINTMSK);
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for (i = 0; i < hsotg->core_params->host_channels; ++i)
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hr->hcintmsk[i] = readl(hsotg->regs + HCINTMSK(i));
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hr->hprt0 = readl(hsotg->regs + HPRT0);
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hr->hfir = readl(hsotg->regs + HFIR);
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return 0;
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}
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/**
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* dwc2_restore_host_registers() - Restore controller host registers.
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* When resuming usb bus, device registers needs to be restored
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* if controller power were disabled.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_hregs_backup *hr;
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int i;
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dev_dbg(hsotg->dev, "%s\n", __func__);
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/* Restore host regs */
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hr = hsotg->hr_backup;
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if (!hr) {
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dev_err(hsotg->dev, "%s: no host registers to restore\n",
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__func__);
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return -EINVAL;
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}
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writel(hr->hcfg, hsotg->regs + HCFG);
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writel(hr->haintmsk, hsotg->regs + HAINTMSK);
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for (i = 0; i < hsotg->core_params->host_channels; ++i)
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writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
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writel(hr->hprt0, hsotg->regs + HPRT0);
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writel(hr->hfir, hsotg->regs + HFIR);
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return 0;
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}
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#else
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static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
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{ return 0; }
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static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
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{ return 0; }
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#endif
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#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
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IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
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/**
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* dwc2_backup_device_registers() - Backup controller device registers.
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* When suspending usb bus, registers needs to be backuped
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* if controller power is disabled once suspended.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_dregs_backup *dr;
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int i;
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dev_dbg(hsotg->dev, "%s\n", __func__);
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/* Backup dev regs */
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dr = hsotg->dr_backup;
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if (!dr) {
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dr = devm_kzalloc(hsotg->dev, sizeof(*dr), GFP_KERNEL);
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if (!dr) {
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dev_err(hsotg->dev, "%s: can't allocate device regs\n",
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__func__);
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return -ENOMEM;
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}
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hsotg->dr_backup = dr;
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}
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dr->dcfg = readl(hsotg->regs + DCFG);
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dr->dctl = readl(hsotg->regs + DCTL);
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dr->daintmsk = readl(hsotg->regs + DAINTMSK);
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dr->diepmsk = readl(hsotg->regs + DIEPMSK);
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dr->doepmsk = readl(hsotg->regs + DOEPMSK);
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for (i = 0; i < hsotg->num_of_eps; i++) {
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/* Backup IN EPs */
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dr->diepctl[i] = readl(hsotg->regs + DIEPCTL(i));
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/* Ensure DATA PID is correctly configured */
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if (dr->diepctl[i] & DXEPCTL_DPID)
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dr->diepctl[i] |= DXEPCTL_SETD1PID;
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else
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dr->diepctl[i] |= DXEPCTL_SETD0PID;
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dr->dieptsiz[i] = readl(hsotg->regs + DIEPTSIZ(i));
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dr->diepdma[i] = readl(hsotg->regs + DIEPDMA(i));
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/* Backup OUT EPs */
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dr->doepctl[i] = readl(hsotg->regs + DOEPCTL(i));
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/* Ensure DATA PID is correctly configured */
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if (dr->doepctl[i] & DXEPCTL_DPID)
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dr->doepctl[i] |= DXEPCTL_SETD1PID;
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else
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dr->doepctl[i] |= DXEPCTL_SETD0PID;
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dr->doeptsiz[i] = readl(hsotg->regs + DOEPTSIZ(i));
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dr->doepdma[i] = readl(hsotg->regs + DOEPDMA(i));
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}
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return 0;
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}
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/**
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* dwc2_restore_device_registers() - Restore controller device registers.
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* When resuming usb bus, device registers needs to be restored
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* if controller power were disabled.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_dregs_backup *dr;
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u32 dctl;
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int i;
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dev_dbg(hsotg->dev, "%s\n", __func__);
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/* Restore dev regs */
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dr = hsotg->dr_backup;
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if (!dr) {
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dev_err(hsotg->dev, "%s: no device registers to restore\n",
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__func__);
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return -EINVAL;
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}
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writel(dr->dcfg, hsotg->regs + DCFG);
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writel(dr->dctl, hsotg->regs + DCTL);
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writel(dr->daintmsk, hsotg->regs + DAINTMSK);
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writel(dr->diepmsk, hsotg->regs + DIEPMSK);
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writel(dr->doepmsk, hsotg->regs + DOEPMSK);
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for (i = 0; i < hsotg->num_of_eps; i++) {
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/* Restore IN EPs */
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writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
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writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
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writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
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/* Restore OUT EPs */
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writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
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writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
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writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
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}
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/* Set the Power-On Programming done bit */
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dctl = readl(hsotg->regs + DCTL);
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dctl |= DCTL_PWRONPRGDONE;
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writel(dctl, hsotg->regs + DCTL);
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return 0;
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}
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#else
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static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
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{ return 0; }
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static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
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{ return 0; }
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#endif
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/**
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* dwc2_backup_global_registers() - Backup global controller registers.
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* When suspending usb bus, registers needs to be backuped
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* if controller power is disabled once suspended.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_gregs_backup *gr;
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int i;
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/* Backup global regs */
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gr = hsotg->gr_backup;
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if (!gr) {
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gr = devm_kzalloc(hsotg->dev, sizeof(*gr), GFP_KERNEL);
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if (!gr) {
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dev_err(hsotg->dev, "%s: can't allocate global regs\n",
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__func__);
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return -ENOMEM;
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}
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hsotg->gr_backup = gr;
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}
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gr->gotgctl = readl(hsotg->regs + GOTGCTL);
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gr->gintmsk = readl(hsotg->regs + GINTMSK);
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gr->gahbcfg = readl(hsotg->regs + GAHBCFG);
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gr->gusbcfg = readl(hsotg->regs + GUSBCFG);
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gr->grxfsiz = readl(hsotg->regs + GRXFSIZ);
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gr->gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ);
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gr->hptxfsiz = readl(hsotg->regs + HPTXFSIZ);
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gr->gdfifocfg = readl(hsotg->regs + GDFIFOCFG);
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for (i = 0; i < MAX_EPS_CHANNELS; i++)
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gr->dtxfsiz[i] = readl(hsotg->regs + DPTXFSIZN(i));
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return 0;
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}
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/**
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* dwc2_restore_global_registers() - Restore controller global registers.
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* When resuming usb bus, device registers needs to be restored
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* if controller power were disabled.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_gregs_backup *gr;
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int i;
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dev_dbg(hsotg->dev, "%s\n", __func__);
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/* Restore global regs */
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gr = hsotg->gr_backup;
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if (!gr) {
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dev_err(hsotg->dev, "%s: no global registers to restore\n",
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__func__);
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return -EINVAL;
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}
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writel(0xffffffff, hsotg->regs + GINTSTS);
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writel(gr->gotgctl, hsotg->regs + GOTGCTL);
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writel(gr->gintmsk, hsotg->regs + GINTMSK);
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writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
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writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
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writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
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writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
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writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
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writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
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for (i = 0; i < MAX_EPS_CHANNELS; i++)
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writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
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return 0;
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}
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/**
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* dwc2_exit_hibernation() - Exit controller from Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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* @restore: Controller registers need to be restored
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*/
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int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
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{
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u32 pcgcctl;
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int ret = 0;
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pcgcctl = readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_STOPPCLK;
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writel(pcgcctl, hsotg->regs + PCGCTL);
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pcgcctl = readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_PWRCLMP;
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writel(pcgcctl, hsotg->regs + PCGCTL);
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pcgcctl = readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
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writel(pcgcctl, hsotg->regs + PCGCTL);
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udelay(100);
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if (restore) {
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ret = dwc2_restore_global_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore registers\n",
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__func__);
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return ret;
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}
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if (dwc2_is_host_mode(hsotg)) {
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ret = dwc2_restore_host_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore host registers\n",
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__func__);
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return ret;
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}
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} else {
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ret = dwc2_restore_device_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore device registers\n",
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__func__);
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return ret;
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}
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}
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}
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return ret;
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}
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/**
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* dwc2_enter_hibernation() - Put controller in Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
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{
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u32 pcgcctl;
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int ret = 0;
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/* Backup all registers */
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ret = dwc2_backup_global_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup global registers\n",
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__func__);
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return ret;
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}
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if (dwc2_is_host_mode(hsotg)) {
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ret = dwc2_backup_host_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup host registers\n",
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__func__);
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return ret;
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}
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} else {
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ret = dwc2_backup_device_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup device registers\n",
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__func__);
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return ret;
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}
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}
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/* Put the controller in low power state */
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pcgcctl = readl(hsotg->regs + PCGCTL);
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pcgcctl |= PCGCTL_PWRCLMP;
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writel(pcgcctl, hsotg->regs + PCGCTL);
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ndelay(20);
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pcgcctl |= PCGCTL_RSTPDWNMODULE;
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writel(pcgcctl, hsotg->regs + PCGCTL);
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ndelay(20);
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pcgcctl |= PCGCTL_STOPPCLK;
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writel(pcgcctl, hsotg->regs + PCGCTL);
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return ret;
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}
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/**
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* dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
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* used in both device and host modes
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@ -451,6 +451,82 @@ struct dwc2_hw_params {
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/* Size of control and EP0 buffers */
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#define DWC2_CTRL_BUFF_SIZE 8
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/**
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* struct dwc2_gregs_backup - Holds global registers state before entering partial
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* power down
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* @gotgctl: Backup of GOTGCTL register
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* @gintmsk: Backup of GINTMSK register
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* @gahbcfg: Backup of GAHBCFG register
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* @gusbcfg: Backup of GUSBCFG register
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* @grxfsiz: Backup of GRXFSIZ register
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* @gnptxfsiz: Backup of GNPTXFSIZ register
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* @gi2cctl: Backup of GI2CCTL register
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* @hptxfsiz: Backup of HPTXFSIZ register
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* @gdfifocfg: Backup of GDFIFOCFG register
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* @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
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* @gpwrdn: Backup of GPWRDN register
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*/
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struct dwc2_gregs_backup {
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u32 gotgctl;
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u32 gintmsk;
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u32 gahbcfg;
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u32 gusbcfg;
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u32 grxfsiz;
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u32 gnptxfsiz;
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u32 gi2cctl;
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u32 hptxfsiz;
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u32 pcgcctl;
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u32 gdfifocfg;
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u32 dtxfsiz[MAX_EPS_CHANNELS];
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u32 gpwrdn;
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};
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/**
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* struct dwc2_dregs_backup - Holds device registers state before entering partial
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* power down
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* @dcfg: Backup of DCFG register
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* @dctl: Backup of DCTL register
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* @daintmsk: Backup of DAINTMSK register
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* @diepmsk: Backup of DIEPMSK register
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* @doepmsk: Backup of DOEPMSK register
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* @diepctl: Backup of DIEPCTL register
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* @dieptsiz: Backup of DIEPTSIZ register
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* @diepdma: Backup of DIEPDMA register
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* @doepctl: Backup of DOEPCTL register
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* @doeptsiz: Backup of DOEPTSIZ register
|
||||
* @doepdma: Backup of DOEPDMA register
|
||||
*/
|
||||
struct dwc2_dregs_backup {
|
||||
u32 dcfg;
|
||||
u32 dctl;
|
||||
u32 daintmsk;
|
||||
u32 diepmsk;
|
||||
u32 doepmsk;
|
||||
u32 diepctl[MAX_EPS_CHANNELS];
|
||||
u32 dieptsiz[MAX_EPS_CHANNELS];
|
||||
u32 diepdma[MAX_EPS_CHANNELS];
|
||||
u32 doepctl[MAX_EPS_CHANNELS];
|
||||
u32 doeptsiz[MAX_EPS_CHANNELS];
|
||||
u32 doepdma[MAX_EPS_CHANNELS];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dwc2_hregs_backup - Holds host registers state before entering partial
|
||||
* power down
|
||||
* @hcfg: Backup of HCFG register
|
||||
* @haintmsk: Backup of HAINTMSK register
|
||||
* @hcintmsk: Backup of HCINTMSK register
|
||||
* @hptr0: Backup of HPTR0 register
|
||||
* @hfir: Backup of HFIR register
|
||||
*/
|
||||
struct dwc2_hregs_backup {
|
||||
u32 hcfg;
|
||||
u32 haintmsk;
|
||||
u32 hcintmsk[MAX_EPS_CHANNELS];
|
||||
u32 hprt0;
|
||||
u32 hfir;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
|
||||
* and periodic schedules
|
||||
|
|
@ -481,6 +557,9 @@ struct dwc2_hw_params {
|
|||
* interrupt
|
||||
* @wkp_timer: Timer object for handling Wakeup Detected interrupt
|
||||
* @lx_state: Lx state of connected device
|
||||
* @gregs_backup: Backup of global registers during suspend
|
||||
* @dregs_backup: Backup of device registers during suspend
|
||||
* @hregs_backup: Backup of host registers during suspend
|
||||
*
|
||||
* These are for host mode:
|
||||
*
|
||||
|
|
@ -613,6 +692,9 @@ struct dwc2_hsotg {
|
|||
struct work_struct wf_otg;
|
||||
struct timer_list wkp_timer;
|
||||
enum dwc2_lx_state lx_state;
|
||||
struct dwc2_gregs_backup *gr_backup;
|
||||
struct dwc2_dregs_backup *dr_backup;
|
||||
struct dwc2_hregs_backup *hr_backup;
|
||||
|
||||
struct dentry *debug_root;
|
||||
struct debugfs_regset32 *regset;
|
||||
|
|
@ -749,6 +831,8 @@ enum dwc2_halt_status {
|
|||
* and the DWC_otg controller
|
||||
*/
|
||||
extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
|
||||
extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
|
||||
extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
|
||||
|
||||
/*
|
||||
* Host core Functions.
|
||||
|
|
|
|||
Loading…
Reference in a new issue