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scsi: ufs: qcom: Perform read back after writing reset bit
[ Upstream commitc4d28e06b0
] Currently, the reset bit for the UFS provided reset controller (used by its phy) is written to, and then a mb() happens to try and ensure that hit the device. Immediately afterwards a usleep_range() occurs. mb() ensures that the write completes, but completion doesn't mean that it isn't stored in a buffer somewhere. The recommendation for ensuring this bit has taken effect on the device is to perform a read back to force it to make it all the way to the device. This is documented in device-io.rst and a talk by Will Deacon on this can be seen over here: https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678 Let's do that to ensure the bit hits the device. By doing so and guaranteeing the ordering against the immediately following usleep_range(), the mb() can safely be removed. Fixes:81c0fc51b7
("ufs-qcom: add support for Qualcomm Technologies Inc platforms") Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20240329-ufs-reset-ensure-effect-before-delay-v5-1-181252004586@redhat.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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parent
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1 changed files with 6 additions and 6 deletions
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@ -156,10 +156,10 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
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1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
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1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
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/*
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/*
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* Make sure assertion of ufs phy reset is written to
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* Dummy read to ensure the write takes effect before doing any sort
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* register before returning
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* of delay
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*/
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*/
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mb();
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ufshcd_readl(hba, REG_UFS_CFG1);
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}
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}
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static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
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static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
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@ -168,10 +168,10 @@ static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
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0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
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0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
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/*
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/*
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* Make sure de-assertion of ufs phy reset is written to
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* Dummy read to ensure the write takes effect before doing any sort
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* register before returning
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* of delay
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*/
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*/
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mb();
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ufshcd_readl(hba, REG_UFS_CFG1);
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}
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}
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/* Host controller hardware version: major.minor.step */
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/* Host controller hardware version: major.minor.step */
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