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Merge branch 'net-ipa-v5.5'

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Alex Elder says:

====================
net: ipa: add IPA v5.5 support

This series adds IPA support for the Qualcomm SM8550 SoC, which uses
IPA v5.5.

The first patch adds a new compatible string for the SM8550.  The
second cleans up "ipa_reg.h" a bit for consistency.  The third patch
adds definitions and some minor code changes related to IPA v5.5.
The fourth defines IPA register offsets and fields used for IPA
v5.0; most--but not all--register definitions are the same as used
in IPA v5.0.  The final patch adds configuration data used for IPA
v5.5 (here again this mostly duplicates IPA v5.0 definitions).
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2023-11-24 12:18:55 +00:00
commit d1d3470a4e
11 changed files with 1130 additions and 62 deletions
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1
Documentation/devicetree/bindings/net/qcom,ipa.yaml
View file

@ -52,6 +52,7 @@ properties:
- qcom,sdx65-ipa
- qcom,sm6350-ipa
- qcom,sm8350-ipa
- qcom,sm8550-ipa
reg:
items:

4
drivers/net/ipa/Makefile
View file

@ -2,12 +2,12 @@
#
# Makefile for the Qualcomm IPA driver.
IPA_REG_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0
IPA_REG_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.5
# Some IPA versions can reuse another set of GSI register definitions.
GSI_REG_VERSIONS := 3.1 3.5.1 4.0 4.5 4.9 4.11 5.0
IPA_DATA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0
IPA_DATA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.5
obj-$(CONFIG_QCOM_IPA) += ipa.o

487
drivers/net/ipa/data/ipa_data-v5.5.c Normal file
View file

@ -0,0 +1,487 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023 Linaro Ltd. */
#include <linux/kernel.h>
#include <linux/log2.h>
#include "../ipa_data.h"
#include "../ipa_endpoint.h"
#include "../ipa_mem.h"
/** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.5 */
enum ipa_resource_type {
/* Source resource types; first must have value 0 */
IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
/* Destination resource types; first must have value 0 */
IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
IPA_RESOURCE_TYPE_DST_DPS_DMARS,
IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS,
};
/* Resource groups used for an SoC having IPA v5.5 */
enum ipa_rsrc_group_id {
/* Source resource group identifiers */
IPA_RSRC_GROUP_SRC_UL = 0,
IPA_RSRC_GROUP_SRC_DL,
IPA_RSRC_GROUP_SRC_UNUSED_2,
IPA_RSRC_GROUP_SRC_UNUSED_3,
IPA_RSRC_GROUP_SRC_URLLC,
IPA_RSRC_GROUP_SRC_U_RX_QC,
IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
/* Destination resource group identifiers */
IPA_RSRC_GROUP_DST_UL = 0,
IPA_RSRC_GROUP_DST_DL,
IPA_RSRC_GROUP_DST_UNUSED_2,
IPA_RSRC_GROUP_DST_UNUSED_3,
IPA_RSRC_GROUP_DST_UNUSED_4,
IPA_RSRC_GROUP_DST_UC,
IPA_RSRC_GROUP_DST_DRB_IP,
IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
};
/* QSB configuration data for an SoC having IPA v5.5 */
static const struct ipa_qsb_data ipa_qsb_data[] = {
[IPA_QSB_MASTER_DDR] = {
.max_writes = 0, /* Unlimited */
.max_reads = 12,
.max_reads_beats = 0,
},
[IPA_QSB_MASTER_PCIE] = {
.max_writes = 0, /* Unlimited */
.max_reads = 8,
.max_reads_beats = 0,
},
};
/* Endpoint configuration data for an SoC having IPA v5.5 */
static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
[IPA_ENDPOINT_AP_COMMAND_TX] = {
.ee_id = GSI_EE_AP,
.channel_id = 12,
.endpoint_id = 14,
.toward_ipa = true,
.channel = {
.tre_count = 256,
.event_count = 256,
.tlv_count = 20,
},
.endpoint = {
.config = {
.resource_group = IPA_RSRC_GROUP_SRC_UL,
.dma_mode = true,
.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
.tx = {
.seq_type = IPA_SEQ_DMA,
},
},
},
},
[IPA_ENDPOINT_AP_LAN_RX] = {
.ee_id = GSI_EE_AP,
.channel_id = 13,
.endpoint_id = 16,
.toward_ipa = false,
.channel = {
.tre_count = 256,
.event_count = 256,
.tlv_count = 9,
},
.endpoint = {
.config = {
.resource_group = IPA_RSRC_GROUP_DST_UL,
.aggregation = true,
.status_enable = true,
.rx = {
.buffer_size = 8192,
.pad_align = ilog2(sizeof(u32)),
.aggr_time_limit = 500,
},
},
},
},
[IPA_ENDPOINT_AP_MODEM_TX] = {
.ee_id = GSI_EE_AP,
.channel_id = 11,
.endpoint_id = 2,
.toward_ipa = true,
.channel = {
.tre_count = 512,
.event_count = 512,
.tlv_count = 25,
},
.endpoint = {
.filter_support = true,
.config = {
.resource_group = IPA_RSRC_GROUP_SRC_UL,
.checksum = true,
.qmap = true,
.status_enable = true,
.tx = {
.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
.status_endpoint =
IPA_ENDPOINT_MODEM_AP_RX,
},
},
},
},
[IPA_ENDPOINT_AP_MODEM_RX] = {
.ee_id = GSI_EE_AP,
.channel_id = 1,
.endpoint_id = 23,
.toward_ipa = false,
.channel = {
.tre_count = 256,
.event_count = 256,
.tlv_count = 9,
},
.endpoint = {
.config = {
.resource_group = IPA_RSRC_GROUP_DST_DL,
.checksum = true,
.qmap = true,
.aggregation = true,
.rx = {
.buffer_size = 8192,
.aggr_time_limit = 500,
.aggr_close_eof = true,
},
},
},
},
[IPA_ENDPOINT_MODEM_AP_TX] = {
.ee_id = GSI_EE_MODEM,
.channel_id = 0,
.endpoint_id = 12,
.toward_ipa = true,
.endpoint = {
.filter_support = true,
},
},
[IPA_ENDPOINT_MODEM_AP_RX] = {
.ee_id = GSI_EE_MODEM,
.channel_id = 7,
.endpoint_id = 21,
.toward_ipa = false,
},
[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
.ee_id = GSI_EE_MODEM,
.channel_id = 2,
.endpoint_id = 15,
.toward_ipa = true,
.endpoint = {
.filter_support = true,
},
},
};
/* Source resource configuration data for an SoC having IPA v5.5 */
static const struct ipa_resource ipa_resource_src[] = {
[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
.limits[IPA_RSRC_GROUP_SRC_UL] = {
.min = 3, .max = 9,
},
.limits[IPA_RSRC_GROUP_SRC_DL] = {
.min = 4, .max = 10,
},
.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
.min = 1, .max = 63,
},
.limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
.min = 0, .max = 63,
},
},
[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
.limits[IPA_RSRC_GROUP_SRC_UL] = {
.min = 9, .max = 9,
},
.limits[IPA_RSRC_GROUP_SRC_DL] = {
.min = 12, .max = 12,
},
.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
.min = 10, .max = 10,
},
},
[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
.limits[IPA_RSRC_GROUP_SRC_UL] = {
.min = 9, .max = 9,
},
.limits[IPA_RSRC_GROUP_SRC_DL] = {
.min = 24, .max = 24,
},
.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
.min = 20, .max = 20,
},
},
[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
.limits[IPA_RSRC_GROUP_SRC_UL] = {
.min = 0, .max = 63,
},
.limits[IPA_RSRC_GROUP_SRC_DL] = {
.min = 0, .max = 63,
},
.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
.min = 1, .max = 63,
},
.limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {
.min = 0, .max = 63,
},
},
[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
.limits[IPA_RSRC_GROUP_SRC_UL] = {
.min = 22, .max = 22,
},
.limits[IPA_RSRC_GROUP_SRC_DL] = {
.min = 16, .max = 16,
},
.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
.min = 16, .max = 16,
},
},
};
/* Destination resource configuration data for an SoC having IPA v5.5 */
static const struct ipa_resource ipa_resource_dst[] = {
[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
.limits[IPA_RSRC_GROUP_DST_UL] = {
.min = 6, .max = 6,
},
.limits[IPA_RSRC_GROUP_DST_DL] = {
.min = 5, .max = 5,
},
.limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
.min = 39, .max = 39,
},
},
[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
.limits[IPA_RSRC_GROUP_DST_UL] = {
.min = 0, .max = 3,
},
.limits[IPA_RSRC_GROUP_DST_DL] = {
.min = 0, .max = 3,
},
},
[IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = {
.limits[IPA_RSRC_GROUP_DST_UL] = {
.min = 0, .max = 63,
},
.limits[IPA_RSRC_GROUP_DST_DL] = {
.min = 0, .max = 63,
},
},
};
/* Resource configuration data for an SoC having IPA v5.5 */
static const struct ipa_resource_data ipa_resource_data = {
.rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
.rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
.resource_src_count = ARRAY_SIZE(ipa_resource_src),
.resource_src = ipa_resource_src,
.resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
.resource_dst = ipa_resource_dst,
};
/* IPA-resident memory region data for an SoC having IPA v5.5 */
static const struct ipa_mem ipa_mem_local_data[] = {
{
.id = IPA_MEM_UC_EVENT_RING,
.offset = 0x0000,
.size = 0x1000,
.canary_count = 0,
},
{
.id = IPA_MEM_UC_SHARED,
.offset = 0x1000,
.size = 0x0080,
.canary_count = 0,
},
{
.id = IPA_MEM_UC_INFO,
.offset = 0x1080,
.size = 0x0200,
.canary_count = 0,
},
{
.id = IPA_MEM_V4_FILTER_HASHED,
.offset = 0x1288,
.size = 0x0078,
.canary_count = 2,
},
{
.id = IPA_MEM_V4_FILTER,
.offset = 0x1308,
.size = 0x0078,
.canary_count = 2,
},
{
.id = IPA_MEM_V6_FILTER_HASHED,
.offset = 0x1388,
.size = 0x0078,
.canary_count = 2,
},
{
.id = IPA_MEM_V6_FILTER,
.offset = 0x1408,
.size = 0x0078,
.canary_count = 2,
},
{
.id = IPA_MEM_V4_ROUTE_HASHED,
.offset = 0x1488,
.size = 0x0098,
.canary_count = 2,
},
{
.id = IPA_MEM_V4_ROUTE,
.offset = 0x1528,
.size = 0x0098,
.canary_count = 2,
},
{
.id = IPA_MEM_V6_ROUTE_HASHED,
.offset = 0x15c8,
.size = 0x0098,
.canary_count = 2,
},
{
.id = IPA_MEM_V6_ROUTE,
.offset = 0x1668,
.size = 0x0098,
.canary_count = 2,
},
{
.id = IPA_MEM_MODEM_HEADER,
.offset = 0x1708,
.size = 0x0240,
.canary_count = 2,
},
{
.id = IPA_MEM_AP_HEADER,
.offset = 0x1948,
.size = 0x01e0,
.canary_count = 0,
},
{
.id = IPA_MEM_MODEM_PROC_CTX,
.offset = 0x1b40,
.size = 0x0b20,
.canary_count = 2,
},
{
.id = IPA_MEM_AP_PROC_CTX,
.offset = 0x2660,
.size = 0x0200,
.canary_count = 0,
},
{
.id = IPA_MEM_STATS_QUOTA_MODEM,
.offset = 0x2868,
.size = 0x0060,
.canary_count = 2,
},
{
.id = IPA_MEM_STATS_QUOTA_AP,
.offset = 0x28c8,
.size = 0x0048,
.canary_count = 0,
},
{
.id = IPA_MEM_STATS_TETHERING,
.offset = 0x2910,
.size = 0x03c0,
.canary_count = 0,
},
{
.id = IPA_MEM_AP_V4_FILTER,
.offset = 0x29b8,
.size = 0x0188,
.canary_count = 2,
},
{
.id = IPA_MEM_AP_V6_FILTER,
.offset = 0x2b40,
.size = 0x0228,
.canary_count = 0,
},
{
.id = IPA_MEM_STATS_FILTER_ROUTE,
.offset = 0x2cd0,
.size = 0x0ba0,
.canary_count = 2,
},
{
.id = IPA_MEM_STATS_DROP,
.offset = 0x3870,
.size = 0x0020,
.canary_count = 0,
},
{
.id = IPA_MEM_MODEM,
.offset = 0x3898,
.size = 0x0d48,
.canary_count = 2,
},
{
.id = IPA_MEM_NAT_TABLE,
.offset = 0x45e0,
.size = 0x0900,
.canary_count = 0,
},
{
.id = IPA_MEM_PDN_CONFIG,
.offset = 0x4ee8,
.size = 0x0100,
.canary_count = 2,
},
};
/* Memory configuration data for an SoC having IPA v5.5 */
static const struct ipa_mem_data ipa_mem_data = {
.local_count = ARRAY_SIZE(ipa_mem_local_data),
.local = ipa_mem_local_data,
.imem_addr = 0x14688000,
.imem_size = 0x00002000,
.smem_id = 497,
.smem_size = 0x0000b000,
};
/* Interconnect rates are in 1000 byte/second units */
static const struct ipa_interconnect_data ipa_interconnect_data[] = {
{
.name = "memory",
.peak_bandwidth = 1900000, /* 1.9 GBps */
.average_bandwidth = 600000, /* 600 MBps */
},
/* Average rate is unused for the next interconnect */
{
.name = "config",
.peak_bandwidth = 76800, /* 76.8 MBps */
.average_bandwidth = 0, /* unused */
},
};
/* Clock and interconnect configuration data for an SoC having IPA v5.5 */
static const struct ipa_power_data ipa_power_data = {
.core_clock_rate = 120 * 1000 * 1000, /* Hz */
.interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
.interconnect_data = ipa_interconnect_data,
};
/* Configuration data for an SoC having IPA v5.5. */
const struct ipa_data ipa_data_v5_5 = {
.version = IPA_VERSION_5_5,
.qsb_count = ARRAY_SIZE(ipa_qsb_data),
.qsb_data = ipa_qsb_data,
.modem_route_count = 11,
.endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
.endpoint_data = ipa_gsi_endpoint_data,
.resource_data = &ipa_resource_data,
.mem_data = &ipa_mem_data,
.power_data = &ipa_power_data,
};

1
drivers/net/ipa/gsi_reg.c
View file

@ -110,6 +110,7 @@ static const struct regs *gsi_regs(struct gsi *gsi)
return &gsi_regs_v4_11;
case IPA_VERSION_5_0:
case IPA_VERSION_5_5:
return &gsi_regs_v5_0;
default:

1
drivers/net/ipa/ipa_data.h
View file

@ -250,5 +250,6 @@ extern const struct ipa_data ipa_data_v4_7;
extern const struct ipa_data ipa_data_v4_9;
extern const struct ipa_data ipa_data_v4_11;
extern const struct ipa_data ipa_data_v5_0;
extern const struct ipa_data ipa_data_v5_5;
#endif /* _IPA_DATA_H_ */

13
drivers/net/ipa/ipa_main.c
View file

@ -74,6 +74,7 @@
#define IPA_PAS_ID 15
/* Shift of 19.2 MHz timestamp to achieve lower resolution timestamps */
/* IPA v5.5+ does not specify Qtime timestamp config for DPL */
#define DPL_TIMESTAMP_SHIFT 14 /* ~1.172 kHz, ~853 usec per tick */
#define TAG_TIMESTAMP_SHIFT 14
#define NAT_TIMESTAMP_SHIFT 24 /* ~1.144 Hz, ~874 msec per tick */
@ -376,9 +377,11 @@ static void ipa_qtime_config(struct ipa *ipa)
iowrite32(0, ipa->reg_virt + reg_offset(reg));
reg = ipa_reg(ipa, QTIME_TIMESTAMP_CFG);
/* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */
val = reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT);
val |= reg_bit(reg, DPL_TIMESTAMP_SEL);
if (ipa->version < IPA_VERSION_5_5) {
/* Set DPL time stamp resolution to use Qtime (not 1 msec) */
val = reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT);
val |= reg_bit(reg, DPL_TIMESTAMP_SEL);
}
/* Configure tag and NAT Qtime timestamp resolution as well */
val = reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT);
val = reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT);
@ -688,6 +691,10 @@ static const struct of_device_id ipa_match[] = {
.compatible = "qcom,sdx65-ipa",
.data = &ipa_data_v5_0,
},
{
.compatible = "qcom,sm8550-ipa",
.data = &ipa_data_v5_5,
},
{ },
};
MODULE_DEVICE_TABLE(of, ipa_match);

2
drivers/net/ipa/ipa_mem.c
View file

@ -165,7 +165,7 @@ static bool ipa_mem_id_valid(struct ipa *ipa, enum ipa_mem_id mem_id)
case IPA_MEM_AP_V4_FILTER:
case IPA_MEM_AP_V6_FILTER:
if (version != IPA_VERSION_5_0)
if (version < IPA_VERSION_5_0)
return false;
break;

6
drivers/net/ipa/ipa_reg.c
View file

@ -44,12 +44,12 @@ static bool ipa_reg_id_valid(struct ipa *ipa, enum ipa_reg_id reg_id)
case DST_RSRC_GRP_45_RSRC_TYPE:
return version <= IPA_VERSION_3_1 ||
version == IPA_VERSION_4_5 ||
version == IPA_VERSION_5_0;
version >= IPA_VERSION_5_0;
case SRC_RSRC_GRP_67_RSRC_TYPE:
case DST_RSRC_GRP_67_RSRC_TYPE:
return version <= IPA_VERSION_3_1 ||
version == IPA_VERSION_5_0;
version >= IPA_VERSION_5_0;
case ENDP_FILTER_ROUTER_HSH_CFG:
return version < IPA_VERSION_5_0 &&
@ -125,6 +125,8 @@ static const struct regs *ipa_regs(enum ipa_version version)
return &ipa_regs_v4_11;
case IPA_VERSION_5_0:
return &ipa_regs_v5_0;
case IPA_VERSION_5_5:
return &ipa_regs_v5_5;
default:
return NULL;
}

111
drivers/net/ipa/ipa_reg.h
View file

@ -240,25 +240,25 @@ enum ipa_reg_local_pkt_proc_cntxt_field_id {
/* COUNTER_CFG register */
enum ipa_reg_counter_cfg_field_id {
EOT_COAL_GRANULARITY, /* Not v3.5+ */
EOT_COAL_GRANULARITY, /* Not IPA v3.5+ */
AGGR_GRANULARITY,
};
/* IPA_TX_CFG register */
enum ipa_reg_ipa_tx_cfg_field_id {
TX0_PREFETCH_DISABLE, /* Not v4.0+ */
TX1_PREFETCH_DISABLE, /* Not v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE, /* Not v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* v4.0+ */
DMAW_SCND_OUTSD_PRED_THRESHOLD, /* v4.0+ */
DMAW_SCND_OUTSD_PRED_EN, /* v4.0+ */
DMAW_MAX_BEATS_256_DIS, /* v4.0+ */
PA_MASK_EN, /* v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* v4.0+ */
DUAL_TX_ENABLE, /* v4.5+ */
SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */
SSPND_PA_NO_BQ_STATE, /* v4.2 only */
HOLB_STICKY_DROP_EN, /* v5.0+ */
TX0_PREFETCH_DISABLE, /* Not IPA v4.0+ */
TX1_PREFETCH_DISABLE, /* Not IPA v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE, /* Not IPA v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* IPA v4.0+ */
DMAW_SCND_OUTSD_PRED_THRESHOLD, /* IPA v4.0+ */
DMAW_SCND_OUTSD_PRED_EN, /* IPA v4.0+ */
DMAW_MAX_BEATS_256_DIS, /* IPA v4.0+ */
PA_MASK_EN, /* IPA v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* IPA v4.0+ */
DUAL_TX_ENABLE, /* IPA v4.5+ */
SSPND_PA_NO_START_STATE, /* IPA v4,2+, not IPA v4.5 */
SSPND_PA_NO_BQ_STATE, /* IPA v4.2 only */
HOLB_STICKY_DROP_EN, /* IPA v5.0+ */
};
/* FLAVOR_0 register */
@ -277,8 +277,8 @@ enum ipa_reg_idle_indication_cfg_field_id {
/* QTIME_TIMESTAMP_CFG register */
enum ipa_reg_qtime_timestamp_cfg_field_id {
DPL_TIMESTAMP_LSB,
DPL_TIMESTAMP_SEL,
DPL_TIMESTAMP_LSB, /* Not IPA v5.5+ */
DPL_TIMESTAMP_SEL, /* Not IPA v5.5+ */
TAG_TIMESTAMP_LSB,
NAT_TIMESTAMP_LSB,
};
@ -319,8 +319,8 @@ enum ipa_reg_rsrc_grp_rsrc_type_field_id {
/* ENDP_INIT_CTRL register */
enum ipa_reg_endp_init_ctrl_field_id {
ENDP_SUSPEND, /* Not v4.0+ */
ENDP_DELAY, /* Not v4.2+ */
ENDP_SUSPEND, /* Not IPA v4.0+ */
ENDP_DELAY, /* Not IPA v4.2+ */
};
/* ENDP_INIT_CFG register */
@ -329,6 +329,7 @@ enum ipa_reg_endp_init_cfg_field_id {
CS_OFFLOAD_EN,
CS_METADATA_HDR_OFFSET,
CS_GEN_QMB_MASTER_SEL,
PIPE_REPLICATE_EN, /* IPA v5.5+ */
};
/** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */
@ -359,11 +360,11 @@ enum ipa_reg_endp_init_hdr_field_id {
HDR_ADDITIONAL_CONST_LEN,
HDR_OFST_PKT_SIZE_VALID,
HDR_OFST_PKT_SIZE,
HDR_A5_MUX, /* Not v4.9+ */
HDR_A5_MUX, /* Not IPA v4.9+ */
HDR_LEN_INC_DEAGG_HDR,
HDR_METADATA_REG_VALID, /* Not v4.5+ */
HDR_LEN_MSB, /* v4.5+ */
HDR_OFST_METADATA_MSB, /* v4.5+ */
HDR_METADATA_REG_VALID, /* Not IPA v4.5+ */
HDR_LEN_MSB, /* IPA v4.5+ */
HDR_OFST_METADATA_MSB, /* IPA v4.5+ */
};
/* ENDP_INIT_HDR_EXT register */
@ -374,23 +375,23 @@ enum ipa_reg_endp_init_hdr_ext_field_id {
HDR_PAYLOAD_LEN_INC_PADDING,
HDR_TOTAL_LEN_OR_PAD_OFFSET,
HDR_PAD_TO_ALIGNMENT,
HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */
HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */
HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */
HDR_BYTES_TO_REMOVE_VALID, /* v5.0+ */
HDR_BYTES_TO_REMOVE, /* v5.0+ */
HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* IPA v4.5+ */
HDR_OFST_PKT_SIZE_MSB, /* IPA v4.5+ */
HDR_ADDITIONAL_CONST_LEN_MSB, /* IPA v4.5+ */
HDR_BYTES_TO_REMOVE_VALID, /* IPA v5.0+ */
HDR_BYTES_TO_REMOVE, /* IPA v5.0+ */
};
/* ENDP_INIT_MODE register */
enum ipa_reg_endp_init_mode_field_id {
ENDP_MODE,
DCPH_ENABLE, /* v4.5+ */
DCPH_ENABLE, /* IPA v4.5+ */
DEST_PIPE_INDEX,
BYTE_THRESHOLD,
PIPE_REPLICATION_EN,
PIPE_REPLICATION_EN, /* Not IPA v5.5+ */
PAD_EN,
HDR_FTCH_DISABLE, /* v4.5+ */
DRBIP_ACL_ENABLE, /* v4.9+ */
HDR_FTCH_DISABLE, /* IPA v4.5+ */
DRBIP_ACL_ENABLE, /* IPA v4.9+ */
};
/** enum ipa_mode - ENDP_INIT_MODE register MODE field value */
@ -412,6 +413,7 @@ enum ipa_reg_endp_init_aggr_field_id {
FORCE_CLOSE,
HARD_BYTE_LIMIT_EN,
AGGR_GRAN_SEL,
AGGR_COAL_L2, /* IPA v5.5+ */
};
/** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */
@ -439,10 +441,10 @@ enum ipa_reg_endp_init_hol_block_en_field_id {
/* ENDP_INIT_HOL_BLOCK_TIMER register */
enum ipa_reg_endp_init_hol_block_timer_field_id {
TIMER_BASE_VALUE, /* Not v4.5+ */
TIMER_SCALE, /* v4.2 only */
TIMER_LIMIT, /* v4.5+ */
TIMER_GRAN_SEL, /* v4.5+ */
TIMER_BASE_VALUE, /* Not IPA v4.5+ */
TIMER_SCALE, /* IPA v4.2 only */
TIMER_LIMIT, /* IPA v4.5+ */
TIMER_GRAN_SEL, /* IPA v4.5+ */
};
/* ENDP_INIT_DEAGGR register */
@ -463,7 +465,7 @@ enum ipa_reg_endp_init_rsrc_grp_field_id {
/* ENDP_INIT_SEQ register */
enum ipa_reg_endp_init_seq_field_id {
SEQ_TYPE,
SEQ_REP_TYPE, /* Not v4.5+ */
SEQ_REP_TYPE, /* Not IPA v4.5+ */
};
/**
@ -512,8 +514,8 @@ enum ipa_seq_rep_type {
enum ipa_reg_endp_status_field_id {
STATUS_EN,
STATUS_ENDP,
STATUS_LOCATION, /* Not v4.5+ */
STATUS_PKT_SUPPRESS, /* v4.0+ */
STATUS_LOCATION, /* Not IPA v4.5+ */
STATUS_PKT_SUPPRESS, /* IPA v4.0+ */
};
/* ENDP_FILTER_ROUTER_HSH_CFG register */
@ -585,11 +587,12 @@ enum ipa_reg_endp_cache_cfg_field_id {
* @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used)
* @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used)
* @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used)
* @IPA_IRQ_ERROR_NON_FATAL: (Not currently used)
* @IPA_IRQ_ERROR_FATAL: (Not currently used)
*/
enum ipa_irq_id {
IPA_IRQ_BAD_SNOC_ACCESS = 0x0,
/* The next bit is not present for IPA v3.5+ */
IPA_IRQ_EOT_COAL = 0x1,
IPA_IRQ_BAD_SNOC_ACCESS = 0x0, /* Not IPA v5.5+ */
IPA_IRQ_EOT_COAL = 0x1, /* Not IPA v3.5+ */
IPA_IRQ_UC_0 = 0x2,
IPA_IRQ_UC_1 = 0x3,
IPA_IRQ_UC_2 = 0x4,
@ -597,11 +600,11 @@ enum ipa_irq_id {
IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6,
IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7,
IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8,
IPA_IRQ_RX_ERR = 0x9,
IPA_IRQ_DEAGGR_ERR = 0xa,
IPA_IRQ_TX_ERR = 0xb,
IPA_IRQ_STEP_MODE = 0xc,
IPA_IRQ_PROC_ERR = 0xd,
IPA_IRQ_RX_ERR = 0x9, /* Not IPA v5.5+ */
IPA_IRQ_DEAGGR_ERR = 0xa, /* Not IPA v5.5+ */
IPA_IRQ_TX_ERR = 0xb, /* Not IPA v5.5+ */
IPA_IRQ_STEP_MODE = 0xc, /* Not IPA v5.5+ */
IPA_IRQ_PROC_ERR = 0xd, /* Not IPA v5.5+ */
IPA_IRQ_TX_SUSPEND = 0xe,
IPA_IRQ_TX_HOLB_DROP = 0xf,
IPA_IRQ_BAM_GSI_IDLE = 0x10,
@ -610,17 +613,16 @@ enum ipa_irq_id {
IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13,
IPA_IRQ_PIPE_RED_ABOVE = 0x14,
IPA_IRQ_UCP = 0x15,
/* The next bit is not present for IPA v4.5+ */
IPA_IRQ_DCMP = 0x16,
IPA_IRQ_DCMP = 0x16, /* Not IPA v4.5+ */
IPA_IRQ_GSI_EE = 0x17,
IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18,
IPA_IRQ_GSI_UC = 0x19,
/* The next bit is present for IPA v4.5+ */
IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a,
/* The next three bits are present for IPA v4.9+ */
IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b,
IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c,
IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d,
IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, /* IPA v4.5-v5.2 */
IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, /* IPA v4.9-v5.2 */
IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, /* IPA v4.9-v5.2 */
IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, /* IPA v4.9-v5.2 */
IPA_IRQ_ERROR_NON_FATAL = 0x1e, /* IPA v5.5+ */
IPA_IRQ_ERROR_FATAL = 0x1f, /* IPA v5.5+ */
IPA_IRQ_COUNT, /* Last; not an id */
};
@ -637,6 +639,7 @@ extern const struct regs ipa_regs_v4_7;
extern const struct regs ipa_regs_v4_9;
extern const struct regs ipa_regs_v4_11;
extern const struct regs ipa_regs_v5_0;
extern const struct regs ipa_regs_v5_5;
const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id);

1
drivers/net/ipa/ipa_version.h
View file

@ -56,6 +56,7 @@ static inline bool ipa_version_supported(enum ipa_version version)
case IPA_VERSION_4_9:
case IPA_VERSION_4_11:
case IPA_VERSION_5_0:
case IPA_VERSION_5_5:
return true;
default:
return false;

565
drivers/net/ipa/reg/ipa_reg-v5.5.c Normal file
View file

@ -0,0 +1,565 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2023 Linaro Ltd. */
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/bits.h>
#include "../ipa_reg.h"
#include "../ipa_version.h"
static const u32 reg_flavor_0_fmask[] = {
[MAX_PIPES] = GENMASK(7, 0),
[MAX_CONS_PIPES] = GENMASK(15, 8),
[MAX_PROD_PIPES] = GENMASK(23, 16),
[PROD_LOWEST] = GENMASK(31, 24),
};
REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
static const u32 reg_comp_cfg_fmask[] = {
[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
[GSI_SNOC_BYPASS_DIS] = BIT(1),
[GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[IPA_QMB_SELECT_CONS_EN] = BIT(5),
[IPA_QMB_SELECT_PROD_EN] = BIT(6),
[GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
/* Bits 17-18 reserved */
[QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
[GENQMB_AOOOWR] = BIT(20),
[IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),
/* Bits 28-29 reserved */
[GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
[GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
};
REG_FIELDS(COMP_CFG, comp_cfg, 0x00000048);
static const u32 reg_clkon_cfg_fmask[] = {
[CLKON_RX] = BIT(0),
[CLKON_PROC] = BIT(1),
[TX_WRAPPER] = BIT(2),
[CLKON_MISC] = BIT(3),
[RAM_ARB] = BIT(4),
[FTCH_HPS] = BIT(5),
[FTCH_DPS] = BIT(6),
[CLKON_HPS] = BIT(7),
[CLKON_DPS] = BIT(8),
[RX_HPS_CMDQS] = BIT(9),
[HPS_DPS_CMDQS] = BIT(10),
[DPS_TX_CMDQS] = BIT(11),
[RSRC_MNGR] = BIT(12),
[CTX_HANDLER] = BIT(13),
[ACK_MNGR] = BIT(14),
[D_DCPH] = BIT(15),
[H_DCPH] = BIT(16),
/* Bit 17 reserved */
[NTF_TX_CMDQS] = BIT(18),
[CLKON_TX_0] = BIT(19),
[CLKON_TX_1] = BIT(20),
[CLKON_FNR] = BIT(21),
[QSB2AXI_CMDQ_L] = BIT(22),
[AGGR_WRAPPER] = BIT(23),
[RAM_SLAVEWAY] = BIT(24),
[CLKON_QMB] = BIT(25),
[WEIGHT_ARB] = BIT(26),
[GSI_IF] = BIT(27),
[CLKON_GLOBAL] = BIT(28),
[GLOBAL_2X_CLK] = BIT(29),
[DPL_FIFO] = BIT(30),
[DRBIP] = BIT(31),
};
REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000050);
static const u32 reg_route_fmask[] = {
[ROUTE_DEF_PIPE] = GENMASK(7, 0),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),
[ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
[ROUTE_DEF_HDR_TABLE] = BIT(26),
[ROUTE_DEF_RETAIN_HDR] = BIT(27),
[ROUTE_DIS] = BIT(28),
/* Bits 29-31 reserved */
};
REG_FIELDS(ROUTE, route, 0x00000054);
static const u32 reg_shared_mem_size_fmask[] = {
[MEM_SIZE] = GENMASK(15, 0),
[MEM_BADDR] = GENMASK(31, 16),
};
REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x0000005c);
static const u32 reg_qsb_max_writes_fmask[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000070);
static const u32 reg_qsb_max_reads_fmask[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-15 reserved */
[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
};
REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000074);
/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000120, 0x0004);
static const u32 reg_filt_rout_cache_flush_fmask[] = {
[ROUTER_CACHE] = BIT(0),
/* Bits 1-3 reserved */
[FILTER_CACHE] = BIT(4),
/* Bits 5-31 reserved */
};
REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
static const u32 reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
[SSPND_PA_NO_START_STATE] = BIT(18),
/* Bit 19 reserved */
[HOLB_STICKY_DROP_EN] = BIT(20),
/* Bits 21-31 reserved */
};
REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
static const u32 reg_idle_indication_cfg_fmask[] = {
[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
[CONST_NON_IDLE_ENABLE] = BIT(16),
/* Bits 17-31 reserved */
};
REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
static const u32 reg_qtime_timestamp_cfg_fmask[] = {
/* Bits 0-7 reserved */
[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
/* Bits 13-15 reserved */
[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
/* Bits 21-31 reserved */
};
REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
[DIV_VALUE] = GENMASK(8, 0),
/* Bits 9-30 reserved */
[DIV_ENABLE] = BIT(31),
};
REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
[PULSE_GRAN_0] = GENMASK(2, 0),
[PULSE_GRAN_1] = GENMASK(5, 3),
[PULSE_GRAN_2] = GENMASK(8, 6),
[PULSE_GRAN_3] = GENMASK(11, 9),
/* Bits 12-31 reserved */
};
REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020);
static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020);
static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020);
static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
0x0000050c, 0x0020);
static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000600, 0x0020);
static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000604, 0x0020);
static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000608, 0x0020);
static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
0x0000060c, 0x0020);
/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
static const u32 reg_endp_init_cfg_fmask[] = {
[FRAG_OFFLOAD_EN] = BIT(0),
[CS_OFFLOAD_EN] = GENMASK(2, 1),
[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
/* Bit 7 reserved */
[CS_GEN_QMB_MASTER_SEL] = BIT(8),
[PIPE_REPLICATE_EN] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
static const u32 reg_endp_init_nat_fmask[] = {
[NAT_EN] = GENMASK(1, 0),
/* Bits 2-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
static const u32 reg_endp_init_hdr_fmask[] = {
[HDR_LEN] = GENMASK(5, 0),
[HDR_OFST_METADATA_VALID] = BIT(6),
[HDR_OFST_METADATA] = GENMASK(12, 7),
[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
[HDR_OFST_PKT_SIZE_VALID] = BIT(19),
[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
/* Bit 26 reserved */
[HDR_LEN_INC_DEAGG_HDR] = BIT(27),
[HDR_LEN_MSB] = GENMASK(29, 28),
[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
static const u32 reg_endp_init_hdr_ext_fmask[] = {
[HDR_ENDIANNESS] = BIT(0),
[HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
[HDR_TOTAL_LEN_OR_PAD] = BIT(2),
[HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
/* Bits 14-15 reserved */
[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
[HDR_BYTES_TO_REMOVE_VALID] = BIT(22),
/* Bit 23 reserved */
[HDR_BYTES_TO_REMOVE] = GENMASK(31, 24),
};
REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
0x00001018, 0x0080);
static const u32 reg_endp_init_mode_fmask[] = {
[ENDP_MODE] = GENMASK(2, 0),
[DCPH_ENABLE] = BIT(3),
[DEST_PIPE_INDEX] = GENMASK(11, 4),
[BYTE_THRESHOLD] = GENMASK(27, 12),
/* Bit 28 reserved */
[PAD_EN] = BIT(29),
[DRBIP_ACL_ENABLE] = BIT(30),
/* Bit 31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
static const u32 reg_endp_init_aggr_fmask[] = {
[AGGR_EN] = GENMASK(1, 0),
[AGGR_TYPE] = GENMASK(4, 2),
[BYTE_LIMIT] = GENMASK(10, 5),
/* Bit 11 reserved */
[TIME_LIMIT] = GENMASK(16, 12),
[PKT_LIMIT] = GENMASK(22, 17),
[SW_EOF_ACTIVE] = BIT(23),
[FORCE_CLOSE] = BIT(24),
/* Bit 25 reserved */
[HARD_BYTE_LIMIT_EN] = BIT(26),
[AGGR_GRAN_SEL] = BIT(27),
[AGGR_COAL_L2] = BIT(28),
/* Bits 27-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
static const u32 reg_endp_init_hol_block_en_fmask[] = {
[HOL_BLOCK_EN] = BIT(0),
/* Bits 1-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
0x0000102c, 0x0080);
static const u32 reg_endp_init_hol_block_timer_fmask[] = {
[TIMER_LIMIT] = GENMASK(4, 0),
/* Bits 5-7 reserved */
[TIMER_GRAN_SEL] = GENMASK(9, 8),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
0x00001030, 0x0080);
static const u32 reg_endp_init_deaggr_fmask[] = {
[DEAGGR_HDR_LEN] = GENMASK(5, 0),
[SYSPIPE_ERR_DETECTION] = BIT(6),
[PACKET_OFFSET_VALID] = BIT(7),
[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
[IGNORE_MIN_PKT_ERR] = BIT(14),
/* Bit 15 reserved */
[MAX_PACKET_LEN] = GENMASK(31, 16),
};
REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
static const u32 reg_endp_init_rsrc_grp_fmask[] = {
[ENDP_RSRC_GRP] = GENMASK(2, 0),
/* Bits 3-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
static const u32 reg_endp_init_seq_fmask[] = {
[SEQ_TYPE] = GENMASK(7, 0),
/* Bits 8-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
static const u32 reg_endp_status_fmask[] = {
[STATUS_EN] = BIT(0),
[STATUS_ENDP] = GENMASK(8, 1),
[STATUS_PKT_SUPPRESS] = BIT(9),
/* Bits 10-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
static const u32 reg_endp_filter_cache_cfg_fmask[] = {
[CACHE_MSK_SRC_ID] = BIT(0),
[CACHE_MSK_SRC_IP] = BIT(1),
[CACHE_MSK_DST_IP] = BIT(2),
[CACHE_MSK_SRC_PORT] = BIT(3),
[CACHE_MSK_DST_PORT] = BIT(4),
[CACHE_MSK_PROTOCOL] = BIT(5),
[CACHE_MSK_METADATA] = BIT(6),
/* Bits 7-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg,
0x0000105c, 0x0080);
static const u32 reg_endp_router_cache_cfg_fmask[] = {
[CACHE_MSK_SRC_ID] = BIT(0),
[CACHE_MSK_SRC_IP] = BIT(1),
[CACHE_MSK_DST_IP] = BIT(2),
[CACHE_MSK_SRC_PORT] = BIT(3),
[CACHE_MSK_DST_PORT] = BIT(4),
[CACHE_MSK_PROTOCOL] = BIT(5),
[CACHE_MSK_METADATA] = BIT(6),
/* Bits 7-31 reserved */
};
REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg,
0x00001060, 0x0080);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
static const u32 reg_ipa_irq_uc_fmask[] = {
[UC_INTR] = BIT(0),
/* Bits 1-31 reserved */
};
REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);
static const struct reg *reg_array[] = {
[COMP_CFG] = &reg_comp_cfg,
[CLKON_CFG] = &reg_clkon_cfg,
[ROUTE] = &reg_route,
[SHARED_MEM_SIZE] = &reg_shared_mem_size,
[QSB_MAX_WRITES] = &reg_qsb_max_writes,
[QSB_MAX_READS] = &reg_qsb_max_reads,
[FILT_ROUT_CACHE_FLUSH] = &reg_filt_rout_cache_flush,
[STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
[LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
[AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
[IPA_TX_CFG] = &reg_ipa_tx_cfg,
[FLAVOR_0] = &reg_flavor_0,
[IDLE_INDICATION_CFG] = &reg_idle_indication_cfg,
[QTIME_TIMESTAMP_CFG] = &reg_qtime_timestamp_cfg,
[TIMERS_XO_CLK_DIV_CFG] = &reg_timers_xo_clk_div_cfg,
[TIMERS_PULSE_GRAN_CFG] = &reg_timers_pulse_gran_cfg,
[SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
[SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
[SRC_RSRC_GRP_45_RSRC_TYPE] = &reg_src_rsrc_grp_45_rsrc_type,
[SRC_RSRC_GRP_67_RSRC_TYPE] = &reg_src_rsrc_grp_67_rsrc_type,
[DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
[DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
[DST_RSRC_GRP_45_RSRC_TYPE] = &reg_dst_rsrc_grp_45_rsrc_type,
[DST_RSRC_GRP_67_RSRC_TYPE] = &reg_dst_rsrc_grp_67_rsrc_type,
[ENDP_INIT_CFG] = &reg_endp_init_cfg,
[ENDP_INIT_NAT] = &reg_endp_init_nat,
[ENDP_INIT_HDR] = &reg_endp_init_hdr,
[ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
[ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
[ENDP_INIT_MODE] = &reg_endp_init_mode,
[ENDP_INIT_AGGR] = &reg_endp_init_aggr,
[ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
[ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
[ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
[ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
[ENDP_INIT_SEQ] = &reg_endp_init_seq,
[ENDP_STATUS] = &reg_endp_status,
[ENDP_FILTER_CACHE_CFG] = &reg_endp_filter_cache_cfg,
[ENDP_ROUTER_CACHE_CFG] = &reg_endp_router_cache_cfg,
[IPA_IRQ_STTS] = &reg_ipa_irq_stts,
[IPA_IRQ_EN] = &reg_ipa_irq_en,
[IPA_IRQ_CLR] = &reg_ipa_irq_clr,
[IPA_IRQ_UC] = &reg_ipa_irq_uc,
[IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
[IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
[IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
};
const struct regs ipa_regs_v5_5 = {
.reg_count = ARRAY_SIZE(reg_array),
.reg = reg_array,
};