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net: phy: dp83826: support TX data voltage tuning
DP83826 offers the possibility to tune the voltage of logical levels of the MLT-3 encoded TX data. This is useful when there is a voltage drop in between the PHY and the connector and we want to increase the voltage levels to compensate for that drop. Prior to PHY configuration, the driver SW resets the PHY which has the same effect as the HW reset pin according to the datasheet. Hence, there's no need to force update the VOD_CFG registers to make sure they hold their reset values. VOD_CFG registers need to be updated only if the DT has been configured with values other than the reset ones. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Catalin Popescu <catalin.popescu@leica-geosystems.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Catalin Popescu
David S. Miller
parent
ed1d7dac08
commit
d1d77120bc
1 changed files with 126 additions and 4 deletions
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@ -12,6 +12,7 @@
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#include <linux/bitfield.h>
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#define DP83822_PHY_ID 0x2000a240
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#define DP83825S_PHY_ID 0x2000a140
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@ -34,6 +35,10 @@
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#define MII_DP83822_GENCFG 0x465
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#define MII_DP83822_SOR1 0x467
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/* DP83826 specific registers */
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#define MII_DP83826_VOD_CFG1 0x30b
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#define MII_DP83826_VOD_CFG2 0x30c
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/* GENCFG */
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#define DP83822_SIG_DET_LOW BIT(0)
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@ -110,6 +115,19 @@
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#define DP83822_RX_ER_STR_MASK GENMASK(9, 8)
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#define DP83822_RX_ER_SHIFT 8
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/* DP83826: VOD_CFG1 & VOD_CFG2 */
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#define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12)
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#define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6)
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#define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12)
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#define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6)
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#define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0)
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#define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4)
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#define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0)
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#define DP83826_CFG_DAC_PERCENT_PER_STEP 625
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#define DP83826_CFG_DAC_PERCENT_DEFAULT 10000
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#define DP83826_CFG_DAC_MINUS_DEFAULT 0x30
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#define DP83826_CFG_DAC_PLUS_DEFAULT 0x10
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#define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \
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ADVERTISED_FIBRE | \
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ADVERTISED_Pause | ADVERTISED_Asym_Pause)
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@ -118,6 +136,8 @@ struct dp83822_private {
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bool fx_signal_det_low;
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int fx_enabled;
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u16 fx_sd_enable;
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u8 cfg_dac_minus;
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u8 cfg_dac_plus;
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};
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static int dp83822_set_wol(struct phy_device *phydev,
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@ -233,7 +253,7 @@ static int dp83822_config_intr(struct phy_device *phydev)
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DP83822_ENERGY_DET_INT_EN |
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DP83822_LINK_QUAL_INT_EN);
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/* Private data pointer is NULL on DP83825/26 */
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/* Private data pointer is NULL on DP83825 */
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if (!dp83822 || !dp83822->fx_enabled)
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misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
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DP83822_DUP_MODE_CHANGE_INT_EN |
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@ -254,7 +274,7 @@ static int dp83822_config_intr(struct phy_device *phydev)
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DP83822_PAGE_RX_INT_EN |
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DP83822_EEE_ERROR_CHANGE_INT_EN);
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/* Private data pointer is NULL on DP83825/26 */
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/* Private data pointer is NULL on DP83825 */
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if (!dp83822 || !dp83822->fx_enabled)
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misr_status |= DP83822_ANEG_ERR_INT_EN |
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DP83822_WOL_PKT_INT_EN;
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@ -474,6 +494,43 @@ static int dp83822_config_init(struct phy_device *phydev)
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return dp8382x_disable_wol(phydev);
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}
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static int dp83826_config_init(struct phy_device *phydev)
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{
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struct dp83822_private *dp83822 = phydev->priv;
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u16 val, mask;
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int ret;
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if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) {
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val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) |
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FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK,
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FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4,
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dp83822->cfg_dac_minus));
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mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK;
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ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG1, mask, val);
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if (ret)
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return ret;
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val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK,
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FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0,
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dp83822->cfg_dac_minus));
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mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK;
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ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
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if (ret)
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return ret;
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}
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if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) {
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val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) |
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FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus);
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mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK;
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ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int dp8382x_config_init(struct phy_device *phydev)
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{
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return dp8382x_disable_wol(phydev);
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@ -509,11 +566,44 @@ static int dp83822_of_init(struct phy_device *phydev)
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return 0;
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}
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static int dp83826_to_dac_minus_one_regval(int percent)
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{
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int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent;
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return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
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}
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static int dp83826_to_dac_plus_one_regval(int percent)
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{
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int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT;
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return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
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}
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static void dp83826_of_init(struct phy_device *phydev)
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{
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struct dp83822_private *dp83822 = phydev->priv;
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struct device *dev = &phydev->mdio.dev;
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u32 val;
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dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT;
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if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val))
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dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val);
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dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT;
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if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val))
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dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val);
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}
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#else
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static int dp83822_of_init(struct phy_device *phydev)
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{
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return 0;
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}
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static void dp83826_of_init(struct phy_device *phydev)
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{
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}
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#endif /* CONFIG_OF_MDIO */
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static int dp83822_read_straps(struct phy_device *phydev)
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@ -567,6 +657,22 @@ static int dp83822_probe(struct phy_device *phydev)
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return 0;
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}
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static int dp83826_probe(struct phy_device *phydev)
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{
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struct dp83822_private *dp83822;
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dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
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GFP_KERNEL);
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if (!dp83822)
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return -ENOMEM;
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phydev->priv = dp83822;
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dp83826_of_init(phydev);
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return 0;
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}
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static int dp83822_suspend(struct phy_device *phydev)
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{
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int value;
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@ -610,6 +716,22 @@ static int dp83822_resume(struct phy_device *phydev)
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.resume = dp83822_resume, \
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}
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#define DP83826_PHY_DRIVER(_id, _name) \
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{ \
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PHY_ID_MATCH_MODEL(_id), \
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.name = (_name), \
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/* PHY_BASIC_FEATURES */ \
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.probe = dp83826_probe, \
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.soft_reset = dp83822_phy_reset, \
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.config_init = dp83826_config_init, \
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.get_wol = dp83822_get_wol, \
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.set_wol = dp83822_set_wol, \
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.config_intr = dp83822_config_intr, \
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.handle_interrupt = dp83822_handle_interrupt, \
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.suspend = dp83822_suspend, \
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.resume = dp83822_resume, \
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}
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#define DP8382X_PHY_DRIVER(_id, _name) \
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{ \
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PHY_ID_MATCH_MODEL(_id), \
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@ -628,8 +750,8 @@ static int dp83822_resume(struct phy_device *phydev)
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static struct phy_driver dp83822_driver[] = {
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DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
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DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
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DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
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DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
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DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
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DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
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DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
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DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
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DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
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