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drm/amd/pp: Remove dead error checking code on Vega10
when smu failed, print out the error info immediately for debug. smum_send_msg_to_smu always return true, so no need to check return value. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
baeb7721b1
commit
d246cd53fd
4 changed files with 67 additions and 142 deletions
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@ -2868,11 +2868,8 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
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(struct vega10_hwmgr *)(hwmgr->backend);
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int tmp_result, result = 0;
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tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
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PP_ASSERT_WITH_CODE(!tmp_result,
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"Failed to configure telemetry!",
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return tmp_result);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_NumOfDisplays, 0);
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@ -2883,13 +2880,9 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
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return 0);
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if ((hwmgr->smu_version == 0x001c2c00) ||
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(hwmgr->smu_version == 0x001c2d00)) {
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tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
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(hwmgr->smu_version == 0x001c2d00))
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_UpdatePkgPwrPidAlpha, 1);
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PP_ASSERT_WITH_CODE(!tmp_result,
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"Failed to set package power PID!",
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return tmp_result);
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}
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tmp_result = vega10_construct_voltage_tables(hwmgr);
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PP_ASSERT_WITH_CODE(!tmp_result,
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@ -3642,12 +3635,9 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
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if (!data->registry_data.sclk_dpm_key_disabled) {
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if (data->smc_state_table.gfx_boot_level !=
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data->dpm_table.gfx_table.dpm_state.soft_min_level) {
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
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hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMinGfxclkByIndex,
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data->smc_state_table.gfx_boot_level),
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"Failed to set soft min sclk index!",
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return -EINVAL);
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data->smc_state_table.gfx_boot_level);
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data->dpm_table.gfx_table.dpm_state.soft_min_level =
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data->smc_state_table.gfx_boot_level;
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}
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@ -3658,19 +3648,13 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
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data->dpm_table.mem_table.dpm_state.soft_min_level) {
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if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
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socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
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hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMinSocclkByIndex,
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socclk_idx),
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"Failed to set soft min uclk index!",
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return -EINVAL);
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socclk_idx);
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} else {
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
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hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMinUclkByIndex,
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data->smc_state_table.mem_boot_level),
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"Failed to set soft min uclk index!",
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return -EINVAL);
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data->smc_state_table.mem_boot_level);
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}
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data->dpm_table.mem_table.dpm_state.soft_min_level =
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data->smc_state_table.mem_boot_level;
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@ -3689,13 +3673,10 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
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if (!data->registry_data.sclk_dpm_key_disabled) {
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if (data->smc_state_table.gfx_max_level !=
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data->dpm_table.gfx_table.dpm_state.soft_max_level) {
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
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hwmgr,
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data->dpm_table.gfx_table.dpm_state.soft_max_level) {
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxGfxclkByIndex,
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data->smc_state_table.gfx_max_level),
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"Failed to set soft max sclk index!",
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return -EINVAL);
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data->smc_state_table.gfx_max_level);
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data->dpm_table.gfx_table.dpm_state.soft_max_level =
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data->smc_state_table.gfx_max_level;
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}
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@ -3703,13 +3684,10 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
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if (!data->registry_data.mclk_dpm_key_disabled) {
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if (data->smc_state_table.mem_max_level !=
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data->dpm_table.mem_table.dpm_state.soft_max_level) {
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
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hwmgr,
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PPSMC_MSG_SetSoftMaxUclkByIndex,
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data->smc_state_table.mem_max_level),
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"Failed to set soft max mclk index!",
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return -EINVAL);
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data->dpm_table.mem_table.dpm_state.soft_max_level) {
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxUclkByIndex,
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data->smc_state_table.mem_max_level);
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data->dpm_table.mem_table.dpm_state.soft_max_level =
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data->smc_state_table.mem_max_level;
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}
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@ -3779,7 +3757,6 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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{
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struct vega10_hwmgr *data =
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(struct vega10_hwmgr *)(hwmgr->backend);
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int result = 0;
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uint32_t low_sclk_interrupt_threshold = 0;
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if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
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@ -3791,12 +3768,12 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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cpu_to_le32(low_sclk_interrupt_threshold);
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/* This message will also enable SmcToHost Interrupt */
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result = smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetLowGfxclkInterruptThreshold,
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(uint32_t)low_sclk_interrupt_threshold);
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}
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return result;
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return 0;
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}
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static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
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@ -3887,11 +3864,7 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
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{
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uint32_t value;
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetCurrPkgPwr),
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"Failed to get current package power!",
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return -EINVAL);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
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vega10_read_arg_from_smc(hwmgr, &value);
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/* power value is an integer */
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@ -3974,10 +3947,10 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
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return ret;
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}
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static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
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static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
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bool has_disp)
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{
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return smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetUclkFastSwitch,
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has_disp ? 0 : 1);
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}
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@ -4012,7 +3985,7 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
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if (!result) {
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clk_request = (clk_freq << 16) | clk_select;
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result = smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_RequestDisplayClockByFreq,
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clk_request);
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}
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@ -4081,10 +4054,9 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
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clock_req.clock_type = amd_pp_dcef_clock;
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clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
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if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
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smum_send_msg_to_smc_with_parameter(
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hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
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min_clocks.dcefClockInSR /100),
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"Attempt to set divider for DCEFCLK Failed!",);
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min_clocks.dcefClockInSR / 100);
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} else {
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pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
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}
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@ -4564,14 +4536,8 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
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if (data->registry_data.sclk_dpm_key_disabled)
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break;
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetCurrentGfxclkIndex),
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"Attempt to get current sclk index Failed!",
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return -1);
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PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
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&now),
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"Attempt to read sclk index Failed!",
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return -1);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
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vega10_read_arg_from_smc(hwmgr, &now);
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for (i = 0; i < sclk_table->count; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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@ -4582,14 +4548,8 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
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if (data->registry_data.mclk_dpm_key_disabled)
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break;
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetCurrentUclkIndex),
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"Attempt to get current mclk index Failed!",
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return -1);
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PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
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&now),
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"Attempt to read mclk index Failed!",
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return -1);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
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vega10_read_arg_from_smc(hwmgr, &now);
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for (i = 0; i < mclk_table->count; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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@ -4597,14 +4557,8 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
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(i == now) ? "*" : "");
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break;
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case PP_PCIE:
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetCurrentLinkIndex),
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"Attempt to get current mclk index Failed!",
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return -1);
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PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
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&now),
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"Attempt to read mclk index Failed!",
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return -1);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
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vega10_read_arg_from_smc(hwmgr, &now);
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for (i = 0; i < pcie_table->count; i++)
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size += sprintf(buf + size, "%d: %s %s\n", i,
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@ -4836,24 +4790,18 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
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if (sclk_idx != ~0) {
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if (!data->registry_data.sclk_dpm_key_disabled)
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PP_ASSERT_WITH_CODE(
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!smum_send_msg_to_smc_with_parameter(
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smum_send_msg_to_smc_with_parameter(
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hwmgr,
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PPSMC_MSG_SetSoftMinGfxclkByIndex,
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sclk_idx),
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"Failed to set soft min sclk index!",
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return -EINVAL);
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sclk_idx);
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}
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if (mclk_idx != ~0) {
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if (!data->registry_data.mclk_dpm_key_disabled)
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PP_ASSERT_WITH_CODE(
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!smum_send_msg_to_smc_with_parameter(
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smum_send_msg_to_smc_with_parameter(
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hwmgr,
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PPSMC_MSG_SetSoftMinUclkByIndex,
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mclk_idx),
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"Failed to set soft min mclk index!",
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return -EINVAL);
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mclk_idx);
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}
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return 0;
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@ -850,7 +850,6 @@ static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const
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static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
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{
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uint32_t data;
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int result;
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uint32_t en = (enable ? 1 : 0);
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uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
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@ -924,11 +923,10 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
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}
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}
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if (enable) {
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/* For Vega10, SMC does not support any mask yet. */
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result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
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PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!");
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}
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/* For Vega10, SMC does not support any mask yet. */
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if (enable)
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smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
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}
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static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
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@ -1344,7 +1342,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
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(struct vega10_hwmgr *)(hwmgr->backend);
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if (data->registry_data.enable_pkg_pwr_tracking_feature)
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return smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetPptLimit, n);
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return 0;
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@ -1406,24 +1404,24 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
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return 0;
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}
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static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
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static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
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uint32_t adjust_percent)
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{
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return smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
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}
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int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
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{
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int adjust_percent, result = 0;
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int adjust_percent;
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if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
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adjust_percent =
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hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
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hwmgr->platform_descriptor.TDPAdjustment :
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(-1 * hwmgr->platform_descriptor.TDPAdjustment);
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result = vega10_set_overdrive_target_percentage(hwmgr,
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vega10_set_overdrive_target_percentage(hwmgr,
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(uint32_t)adjust_percent);
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}
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return result;
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return 0;
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}
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@ -31,14 +31,8 @@
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static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
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{
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetCurrentRpm),
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"Attempt to get current RPM from SMC Failed!",
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return -1);
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PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
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current_rpm),
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"Attempt to read current RPM from SMC Failed!",
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return -1);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm);
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vega10_read_arg_from_smc(hwmgr, current_rpm);
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return 0;
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}
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@ -228,20 +228,15 @@ int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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"Invalid SMU Table version!", return -EINVAL);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
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"Invalid SMU Table Length!", return -EINVAL);
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PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
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vega10_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrHigh,
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priv->smu_tables.entry[table_id].table_addr_high) == 0,
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"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL);
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PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
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priv->smu_tables.entry[table_id].table_addr_high);
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vega10_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrLow,
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priv->smu_tables.entry[table_id].table_addr_low) == 0,
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"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
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return -EINVAL);
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PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
priv->smu_tables.entry[table_id].table_addr_low);
|
||||
vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_TransferTableSmu2Dram,
|
||||
priv->smu_tables.entry[table_id].table_id) == 0,
|
||||
"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
|
||||
return -EINVAL);
|
||||
priv->smu_tables.entry[table_id].table_id);
|
||||
|
||||
memcpy(table, priv->smu_tables.entry[table_id].table,
|
||||
priv->smu_tables.entry[table_id].size);
|
||||
|
@ -270,21 +265,15 @@ int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
|
|||
memcpy(priv->smu_tables.entry[table_id].table, table,
|
||||
priv->smu_tables.entry[table_id].size);
|
||||
|
||||
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_SetDriverDramAddrHigh,
|
||||
priv->smu_tables.entry[table_id].table_addr_high) == 0,
|
||||
"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
|
||||
return -EINVAL;);
|
||||
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
priv->smu_tables.entry[table_id].table_addr_high);
|
||||
vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_SetDriverDramAddrLow,
|
||||
priv->smu_tables.entry[table_id].table_addr_low) == 0,
|
||||
"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
|
||||
return -EINVAL);
|
||||
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
priv->smu_tables.entry[table_id].table_addr_low);
|
||||
vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_TransferTableDram2Smu,
|
||||
priv->smu_tables.entry[table_id].table_id) == 0,
|
||||
"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
|
||||
return -EINVAL);
|
||||
priv->smu_tables.entry[table_id].table_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -323,13 +312,9 @@ int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
|
|||
if (features_enabled == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
if (!vega10_send_msg_to_smc(hwmgr,
|
||||
PPSMC_MSG_GetEnabledSmuFeatures)) {
|
||||
vega10_read_arg_from_smc(hwmgr, features_enabled);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
vega10_send_msg_to_smc(hwmgr, PPSMC_MSG_GetEnabledSmuFeatures);
|
||||
vega10_read_arg_from_smc(hwmgr, features_enabled);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
|
||||
|
@ -339,12 +324,12 @@ int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
|
|||
|
||||
if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high ||
|
||||
priv->smu_tables.entry[TOOLSTABLE].table_addr_low) {
|
||||
if (!vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_SetToolsDramAddrHigh,
|
||||
priv->smu_tables.entry[TOOLSTABLE].table_addr_high))
|
||||
vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_SetToolsDramAddrLow,
|
||||
priv->smu_tables.entry[TOOLSTABLE].table_addr_low);
|
||||
priv->smu_tables.entry[TOOLSTABLE].table_addr_high);
|
||||
vega10_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_SetToolsDramAddrLow,
|
||||
priv->smu_tables.entry[TOOLSTABLE].table_addr_low);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue