mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-08-24 09:50:04 +00:00
Code Issues Releases Wiki Activity

xtensa: fix a7 clobbering in coprocessor context load/store

Browse source 
commit 839769c354 upstream.

Fast coprocessor exception handler saves a3..a6, but coprocessor context
load/store code uses a4..a7 as temporaries, potentially clobbering a7.
'Potentially' because coprocessor state load/store macros may not use
all four temporary registers (and neither FPU nor HiFi macros do).
Use a3..a6 as intended.

Cc: stable@vger.kernel.org
Fixes: c658eac628 ("[XTENSA] Add support for configurable registers and coprocessors")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Max Filippov 2022-04-13 22:44:36 -07:00 committed by Greg Kroah-Hartman
parent 4c26a96d0c
commit d24e0d9d69
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/xtensa/kernel/coprocessor.S
View file

@ -37,7 +37,7 @@
.if XTENSA_HAVE_COPROCESSOR(x); \
.align 4; \
.Lsave_cp_regs_cp##x: \
xchal_cp##x##_store a2 a4 a5 a6 a7; \
xchal_cp##x##_store a2 a3 a4 a5 a6; \
jx a0; \
.endif
@ -54,7 +54,7 @@
.if XTENSA_HAVE_COPROCESSOR(x); \
.align 4; \
.Lload_cp_regs_cp##x: \
xchal_cp##x##_load a2 a4 a5 a6 a7; \
xchal_cp##x##_load a2 a3 a4 a5 a6; \
jx a0; \
.endif