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drm/amdgpu/vcn2.5: add DPG mode start and stop
Add DPG mode start and stop functions for vcn2.5 v2: Correct firmware ucode index in vcn_v2_5_mc_resume_dpg_mode Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu
Alex Deucher
parent
45cec87cd6
commit
d2a2c64f53
1 changed files with 288 additions and 2 deletions
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@ -286,7 +286,8 @@ static int vcn_v2_5_hw_init(void *handle)
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done:
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if (!r)
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DRM_INFO("VCN decode and encode initialized successfully.\n");
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DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
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(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
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return r;
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}
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@ -309,7 +310,9 @@ static int vcn_v2_5_hw_fini(void *handle)
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continue;
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ring = &adev->vcn.inst[i].ring_dec;
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if (RREG32_SOC15(VCN, i, mmUVD_STATUS))
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if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
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(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
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RREG32_SOC15(VCN, i, mmUVD_STATUS)))
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vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
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ring->sched.ready = false;
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@ -418,6 +421,78 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
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}
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}
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static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
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{
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uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
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uint32_t offset;
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/* cache window 0: fw */
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
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offset = 0;
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} else {
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
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offset = size;
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
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AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
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}
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
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/* cache window 1: stack */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
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lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
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upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
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/* cache window 2: context */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
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lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
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upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
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/* non-cache window */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
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/* VCN global tiling registers */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
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}
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/**
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* vcn_v2_5_disable_clock_gating - disable VCN clock gating
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*
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@ -536,6 +611,54 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
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}
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}
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static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
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uint8_t sram_sel, int inst_idx, uint8_t indirect)
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{
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uint32_t reg_data = 0;
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/* enable sw clock gating control */
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if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
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reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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else
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reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
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UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
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UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
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UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
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UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
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UVD_CGC_CTRL__SYS_MODE_MASK |
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UVD_CGC_CTRL__UDEC_MODE_MASK |
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UVD_CGC_CTRL__MPEG2_MODE_MASK |
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UVD_CGC_CTRL__REGS_MODE_MASK |
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UVD_CGC_CTRL__RBC_MODE_MASK |
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UVD_CGC_CTRL__LMI_MC_MODE_MASK |
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UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
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UVD_CGC_CTRL__IDCT_MODE_MASK |
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UVD_CGC_CTRL__MPRD_MODE_MASK |
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UVD_CGC_CTRL__MPC_MODE_MASK |
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UVD_CGC_CTRL__LBSI_MODE_MASK |
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UVD_CGC_CTRL__LRBBM_MODE_MASK |
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UVD_CGC_CTRL__WCB_MODE_MASK |
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UVD_CGC_CTRL__VCPU_MODE_MASK |
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UVD_CGC_CTRL__MMSCH_MODE_MASK);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
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/* turn off clock gating */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
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/* turn on SUVD clock gating */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
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/* turn on sw mode in UVD_SUVD_CGC_CTRL */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
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}
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/**
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* vcn_v2_5_enable_clock_gating - enable VCN clock gating
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*
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@ -598,6 +721,130 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
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}
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}
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static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
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{
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struct amdgpu_ring *ring;
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uint32_t rb_bufsz, tmp;
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/* disable register anti-hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 1,
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~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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/* enable dynamic power gating mode */
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tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_POWER_STATUS);
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tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
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tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
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WREG32_SOC15(UVD, inst_idx, mmUVD_POWER_STATUS, tmp);
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/* enable clock gating */
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vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
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/* enable VCPU clock */
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tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
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tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
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tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
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/* disable master interupt */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
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/* setup mmUVD_LMI_CTRL */
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tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
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UVD_LMI_CTRL__REQ_MODE_MASK |
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UVD_LMI_CTRL__CRC_RESET_MASK |
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UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
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UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
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UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
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(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
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0x00100000L);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_MPC_CNTL),
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0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
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((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
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(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
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(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
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((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
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(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
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(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_MPC_SET_MUX),
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((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
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(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
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vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
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/* enable LMI MC and UMC channels */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
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/* unblock VCPU register access */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
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tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
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tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
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/* enable master interrupt */
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WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
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UVD, inst_idx, mmUVD_MASTINT_EN),
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UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
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ring = &adev->vcn.inst[inst_idx].ring_dec;
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/* force RBC into idle state */
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rb_bufsz = order_base_2(ring->ring_size);
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tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
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WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
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/* set the write pointer delay */
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WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
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/* set the wb address */
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WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
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(upper_32_bits(ring->gpu_addr) >> 2));
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/* programm the RB_BASE for ring buffer */
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WREG32_SOC15(UVD, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
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lower_32_bits(ring->gpu_addr));
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WREG32_SOC15(UVD, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
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upper_32_bits(ring->gpu_addr));
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/* Initialize the ring buffer's read and write pointers */
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WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_RPTR, 0);
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WREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2, 0);
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ring->wptr = RREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_RPTR);
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WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,
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lower_32_bits(ring->wptr));
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return 0;
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}
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static int vcn_v2_5_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring;
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@ -610,6 +857,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
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return vcn_v2_5_start_dpg_mode(adev, i, 0);
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/* disable register anti-hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
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~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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@ -973,6 +1223,35 @@ static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
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return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table);
|
||||
}
|
||||
|
||||
static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
|
||||
{
|
||||
int ret_code = 0;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Wait for power status to be 1 */
|
||||
SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
|
||||
/* wait for read ptr to be equal to write ptr */
|
||||
tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR);
|
||||
SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
|
||||
tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR2);
|
||||
SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
|
||||
|
||||
tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
|
||||
SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
|
||||
SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
|
||||
/* disable dynamic power gating mode */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 0,
|
||||
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vcn_v2_5_stop(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
|
@ -981,6 +1260,12 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
|
|||
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
|
||||
if (adev->vcn.harvest_config & (1 << i))
|
||||
continue;
|
||||
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
|
||||
r = vcn_v2_5_stop_dpg_mode(adev, i);
|
||||
goto power_off;
|
||||
}
|
||||
|
||||
/* wait for vcn idle */
|
||||
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
|
||||
if (r)
|
||||
|
|
@ -1030,6 +1315,7 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
|
|||
~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
}
|
||||
|
||||
power_off:
|
||||
if (adev->pm.dpm_enabled)
|
||||
amdgpu_dpm_enable_uvd(adev, false);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue