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drm/i915: Parametrize CSR_PROGRAM registers
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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1 changed files with 3 additions and 4 deletions
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@ -50,7 +50,7 @@ MODULE_FIRMWARE(I915_CSR_BXT);
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/*
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/*
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* SKL CSR registers for DC5 and DC6
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* SKL CSR registers for DC5 and DC6
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*/
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*/
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#define CSR_PROGRAM_BASE 0x80000
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#define CSR_PROGRAM(i) (0x80000 + (i) * 4)
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#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
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#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
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#define CSR_HTP_ADDR_SKL 0x00500034
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#define CSR_HTP_ADDR_SKL 0x00500034
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#define CSR_SSP_BASE 0x8F074
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#define CSR_SSP_BASE 0x8F074
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@ -268,8 +268,7 @@ void intel_csr_load_program(struct drm_device *dev)
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mutex_lock(&dev_priv->csr_lock);
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mutex_lock(&dev_priv->csr_lock);
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fw_size = dev_priv->csr.dmc_fw_size;
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fw_size = dev_priv->csr.dmc_fw_size;
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for (i = 0; i < fw_size; i++)
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for (i = 0; i < fw_size; i++)
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I915_WRITE(CSR_PROGRAM_BASE + i * 4,
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I915_WRITE(CSR_PROGRAM(i), payload[i]);
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payload[i]);
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for (i = 0; i < dev_priv->csr.mmio_count; i++) {
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for (i = 0; i < dev_priv->csr.mmio_count; i++) {
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I915_WRITE(dev_priv->csr.mmioaddr[i],
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I915_WRITE(dev_priv->csr.mmioaddr[i],
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@ -471,7 +470,7 @@ void assert_csr_loaded(struct drm_i915_private *dev_priv)
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{
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{
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WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
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WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
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"CSR is not loaded.\n");
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"CSR is not loaded.\n");
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WARN_ONCE(!I915_READ(CSR_PROGRAM_BASE),
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WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
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"CSR program storage start is NULL\n");
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"CSR program storage start is NULL\n");
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WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
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WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
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WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
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WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
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