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iommu/mediatek: Contain MM IOMMU flow with the MM TYPE
Prepare for supporting INFRA_IOMMU, and APU_IOMMU later. For Infra IOMMU/APU IOMMU, it doesn't have the "larb""port". thus, Use the MM flag contain the MM_IOMMU special flow, Also, it moves a big chunk code about parsing the mediatek,larbs into a function, this is only needed for MM IOMMU. and all the current SoC are MM_IOMMU. The device link between iommu consumer device and smi-larb device only is needed in MM iommu case. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20220503071427.2285-18-yong.wu@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Yong Wu
Joerg Roedel
parent
8cd1e619e7
commit
d2e9a1102c
1 changed files with 122 additions and 91 deletions
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@ -138,6 +138,8 @@
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#define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\
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MTK_IOMMU_TYPE_MASK)
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#define MTK_INVALID_LARBID MTK_LARB_NR_MAX
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struct mtk_iommu_domain {
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struct io_pgtable_cfg cfg;
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struct io_pgtable_ops *iop;
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@ -274,7 +276,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
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{
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struct mtk_iommu_data *data = dev_id;
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struct mtk_iommu_domain *dom = data->m4u_dom;
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unsigned int fault_larb, fault_port, sub_comm = 0;
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unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0;
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u32 int_state, regval, va34_32, pa34_32;
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u64 fault_iova, fault_pa;
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bool layer, write;
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@ -300,17 +302,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
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pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
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fault_pa |= (u64)pa34_32 << 32;
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fault_port = F_MMU_INT_ID_PORT_ID(regval);
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if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM_2BITS)) {
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fault_larb = F_MMU_INT_ID_COMM_ID(regval);
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sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
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} else if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM_3BITS)) {
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fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
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sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
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} else {
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fault_larb = F_MMU_INT_ID_LARB_ID(regval);
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if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
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fault_port = F_MMU_INT_ID_PORT_ID(regval);
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if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM_2BITS)) {
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fault_larb = F_MMU_INT_ID_COMM_ID(regval);
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sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
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} else if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM_3BITS)) {
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fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
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sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
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} else {
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fault_larb = F_MMU_INT_ID_LARB_ID(regval);
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}
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fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
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}
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fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
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if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
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write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
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@ -374,19 +378,21 @@ static void mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
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larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
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portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
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larb_mmu = &data->larb_imu[larbid];
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if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
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larb_mmu = &data->larb_imu[larbid];
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region = data->plat_data->iova_region + domid;
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larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
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region = data->plat_data->iova_region + domid;
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larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
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dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n",
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enable ? "enable" : "disable", dev_name(larb_mmu->dev),
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portid, domid, larb_mmu->bank[portid]);
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dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n",
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enable ? "enable" : "disable", dev_name(larb_mmu->dev),
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portid, domid, larb_mmu->bank[portid]);
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if (enable)
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larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
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else
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larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
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if (enable)
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larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
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else
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larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
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}
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}
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}
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@ -593,6 +599,9 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
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data = dev_iommu_priv_get(dev);
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if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
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return &data->iommu;
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/*
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* Link the consumer device with the smi-larb device(supplier).
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* The device that connects with each a larb is a independent HW.
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@ -626,9 +635,11 @@ static void mtk_iommu_release_device(struct device *dev)
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return;
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data = dev_iommu_priv_get(dev);
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larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
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larbdev = data->larb_imu[larbid].dev;
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device_link_remove(dev, larbdev);
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if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
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larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
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larbdev = data->larb_imu[larbid].dev;
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device_link_remove(dev, larbdev);
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}
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iommu_fwspec_free(dev);
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}
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@ -820,19 +831,77 @@ static const struct component_master_ops mtk_iommu_com_ops = {
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.unbind = mtk_iommu_unbind,
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};
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static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match,
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struct mtk_iommu_data *data)
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{
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struct device_node *larbnode, *smicomm_node;
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struct platform_device *plarbdev;
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struct device_link *link;
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int i, larb_nr, ret;
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larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL);
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if (larb_nr < 0)
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return larb_nr;
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for (i = 0; i < larb_nr; i++) {
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u32 id;
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larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
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if (!larbnode)
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return -EINVAL;
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if (!of_device_is_available(larbnode)) {
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of_node_put(larbnode);
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continue;
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}
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ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
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if (ret)/* The id is consecutive if there is no this property */
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id = i;
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plarbdev = of_find_device_by_node(larbnode);
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if (!plarbdev) {
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of_node_put(larbnode);
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return -ENODEV;
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}
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if (!plarbdev->dev.driver) {
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of_node_put(larbnode);
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return -EPROBE_DEFER;
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}
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data->larb_imu[id].dev = &plarbdev->dev;
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component_match_add_release(dev, match, component_release_of,
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component_compare_of, larbnode);
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}
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/* Get smi-common dev from the last larb. */
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smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
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if (!smicomm_node)
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return -EINVAL;
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plarbdev = of_find_device_by_node(smicomm_node);
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of_node_put(smicomm_node);
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data->smicomm_dev = &plarbdev->dev;
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link = device_link_add(data->smicomm_dev, dev,
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DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
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if (!link) {
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dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
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return -EINVAL;
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}
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return 0;
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}
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static int mtk_iommu_probe(struct platform_device *pdev)
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{
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struct mtk_iommu_data *data;
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struct device *dev = &pdev->dev;
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struct device_node *larbnode, *smicomm_node;
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struct platform_device *plarbdev;
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struct device_link *link;
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struct resource *res;
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resource_size_t ioaddr;
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struct component_match *match = NULL;
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struct regmap *infracfg;
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void *protect;
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int i, larb_nr, ret;
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int ret;
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u32 val;
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char *p;
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@ -887,59 +956,14 @@ static int mtk_iommu_probe(struct platform_device *pdev)
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return PTR_ERR(data->bclk);
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}
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larb_nr = of_count_phandle_with_args(dev->of_node,
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"mediatek,larbs", NULL);
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if (larb_nr < 0)
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return larb_nr;
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for (i = 0; i < larb_nr; i++) {
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u32 id;
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larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
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if (!larbnode)
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return -EINVAL;
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if (!of_device_is_available(larbnode)) {
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of_node_put(larbnode);
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continue;
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}
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ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
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if (ret)/* The id is consecutive if there is no this property */
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id = i;
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plarbdev = of_find_device_by_node(larbnode);
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if (!plarbdev) {
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of_node_put(larbnode);
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return -ENODEV;
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}
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if (!plarbdev->dev.driver) {
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of_node_put(larbnode);
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return -EPROBE_DEFER;
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}
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data->larb_imu[id].dev = &plarbdev->dev;
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component_match_add_release(dev, &match, component_release_of,
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component_compare_of, larbnode);
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}
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/* Get smi-common dev from the last larb. */
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smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
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if (!smicomm_node)
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return -EINVAL;
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plarbdev = of_find_device_by_node(smicomm_node);
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of_node_put(smicomm_node);
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data->smicomm_dev = &plarbdev->dev;
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pm_runtime_enable(dev);
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link = device_link_add(data->smicomm_dev, dev,
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DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
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if (!link) {
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dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
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ret = -EINVAL;
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goto out_runtime_disable;
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if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
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ret = mtk_iommu_mm_dts_parse(dev, &match, data);
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if (ret) {
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dev_err(dev, "mm dts parse fail(%d).", ret);
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goto out_runtime_disable;
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}
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}
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platform_set_drvdata(pdev, data);
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@ -971,9 +995,11 @@ static int mtk_iommu_probe(struct platform_device *pdev)
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goto out_list_del;
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}
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ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
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if (ret)
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goto out_bus_set_null;
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if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
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ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
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if (ret)
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goto out_bus_set_null;
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}
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return ret;
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out_bus_set_null:
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@ -984,7 +1010,8 @@ static int mtk_iommu_probe(struct platform_device *pdev)
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out_sysfs_remove:
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iommu_device_sysfs_remove(&data->iommu);
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out_link_remove:
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device_link_remove(data->smicomm_dev, dev);
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if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
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device_link_remove(data->smicomm_dev, dev);
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out_runtime_disable:
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pm_runtime_disable(dev);
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return ret;
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@ -999,10 +1026,12 @@ static int mtk_iommu_remove(struct platform_device *pdev)
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list_del(&data->list);
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device_link_remove(data->smicomm_dev, &pdev->dev);
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if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
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device_link_remove(data->smicomm_dev, &pdev->dev);
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component_master_del(&pdev->dev, &mtk_iommu_com_ops);
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}
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pm_runtime_disable(&pdev->dev);
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devm_free_irq(&pdev->dev, data->irq, data);
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component_master_del(&pdev->dev, &mtk_iommu_com_ops);
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return 0;
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}
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@ -1072,7 +1101,8 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
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static const struct mtk_iommu_plat_data mt2712_data = {
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.m4u_plat = M4U_MT2712,
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.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE,
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.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
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MTK_IOMMU_TYPE_MM,
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.hw_list = &m4ulist,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.iova_region = single_domain,
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@ -1082,7 +1112,8 @@ static const struct mtk_iommu_plat_data mt2712_data = {
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static const struct mtk_iommu_plat_data mt6779_data = {
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.m4u_plat = M4U_MT6779,
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.flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN,
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.flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
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MTK_IOMMU_TYPE_MM,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
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.iova_region = single_domain,
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.iova_region_nr = ARRAY_SIZE(single_domain),
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@ -1091,7 +1122,7 @@ static const struct mtk_iommu_plat_data mt6779_data = {
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static const struct mtk_iommu_plat_data mt8167_data = {
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.m4u_plat = M4U_MT8167,
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.flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR,
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.flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.iova_region = single_domain,
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.iova_region_nr = ARRAY_SIZE(single_domain),
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@ -1101,7 +1132,7 @@ static const struct mtk_iommu_plat_data mt8167_data = {
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static const struct mtk_iommu_plat_data mt8173_data = {
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.m4u_plat = M4U_MT8173,
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.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
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HAS_LEGACY_IVRP_PADDR,
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HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.iova_region = single_domain,
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.iova_region_nr = ARRAY_SIZE(single_domain),
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@ -1110,7 +1141,7 @@ static const struct mtk_iommu_plat_data mt8173_data = {
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static const struct mtk_iommu_plat_data mt8183_data = {
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.m4u_plat = M4U_MT8183,
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.flags = RESET_AXI,
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.flags = RESET_AXI | MTK_IOMMU_TYPE_MM,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.iova_region = single_domain,
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.iova_region_nr = ARRAY_SIZE(single_domain),
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@ -1120,7 +1151,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
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static const struct mtk_iommu_plat_data mt8192_data = {
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.m4u_plat = M4U_MT8192,
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.flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
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WR_THROT_EN | IOVA_34_EN,
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WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
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.iova_region = mt8192_multi_dom,
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.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
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