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arm64: dts: qcom: sm8450: switch to usb3/dp combo phy
The QMP PHY is a USB3/DP combo phy, switch to the newly documented bindings and register the clocks to the GCC and DISPCC controllers. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-4-d78313cbc41d@linaro.org
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1 changed files with 15 additions and 27 deletions
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@ -11,6 +11,7 @@
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/phy/phy-qcom-qmp.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/interconnect/qcom,sm8450.h>
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#include <dt-bindings/soc/qcom,gpr.h>
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@ -747,7 +748,7 @@ gcc: clock-controller@100000 {
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<&ufs_mem_phy_lanes 0>,
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<&ufs_mem_phy_lanes 1>,
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<&ufs_mem_phy_lanes 2>,
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<0>;
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<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
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clock-names = "bi_tcxo",
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"sleep_clk",
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"pcie_0_pipe_clk",
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@ -2033,37 +2034,24 @@ usb_1_hsphy: phy@88e3000 {
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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};
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usb_1_qmpphy: phy-wrapper@88e9000 {
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compatible = "qcom,sm8450-qmp-usb3-phy";
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reg = <0 0x088e9000 0 0x200>,
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<0 0x088e8000 0 0x20>;
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status = "disabled";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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usb_1_qmpphy: phy@88e8000 {
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compatible = "qcom,sm8450-qmp-usb3-dp-phy";
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reg = <0 0x088e8000 0 0x3000>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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clock-names = "aux", "ref_clk_src", "com_aux";
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "aux", "ref", "com_aux", "usb3_pipe";
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resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_PHY_PRIM_BCR>;
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reset-names = "phy", "common";
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usb_1_ssphy: phy@88e9200 {
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reg = <0 0x088e9200 0 0x200>,
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<0 0x088e9400 0 0x200>,
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<0 0x088e9c00 0 0x400>,
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<0 0x088e9600 0 0x200>,
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<0 0x088e9800 0 0x200>,
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<0 0x088e9a00 0 0x100>;
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_phy_pipe_clk_src";
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};
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#clock-cells = <1>;
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#phy-cells = <1>;
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status = "disabled";
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};
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remoteproc_slpi: remoteproc@2400000 {
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@ -2970,8 +2958,8 @@ dispcc: clock-controller@af00000 {
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<&mdss_dsi0_phy 1>,
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<&mdss_dsi1_phy 0>,
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<&mdss_dsi1_phy 1>,
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<0>, /* dp0 */
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<0>,
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<&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
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<0>, /* dp1 */
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<0>,
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<0>, /* dp2 */
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@ -4167,7 +4155,7 @@ usb_1_dwc3: usb@a600000 {
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iommus = <&apps_smmu 0x0 0x0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
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phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
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phy-names = "usb2-phy", "usb3-phy";
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ports {
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