mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-03 17:40:04 +00:00
Merge branch 'next-i2c' of git://aeryn.fluff.org.uk/bjdooks/linux
* 'next-i2c' of git://aeryn.fluff.org.uk/bjdooks/linux: i2c-ocores: Can add I2C devices to the bus i2c-s3c2410: move to using platform idtable to match devices i2c: OMAP3: Better noise suppression for fast/standard modes i2c: OMAP2/3: Fix scll/sclh calculations i2c: Blackfin TWI: implement I2C_FUNC_SMBUS_I2C_BLOCK functionality i2c: Blackfin TWI: fix transfer errors with repeat start i2c: Blackfin TWI: fix REPEAT START mode doesn't repeat i2c: Blackfin TWI: make sure we don't end up with a CLKDIV=0
This commit is contained in:
commit
d32f60ed54
7 changed files with 118 additions and 54 deletions
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@ -20,6 +20,8 @@ platform_device with the base address and interrupt number. The
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dev.platform_data of the device should also point to a struct
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ocores_i2c_platform_data (see linux/i2c-ocores.h) describing the
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distance between registers and the input clock speed.
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There is also a possibility to attach a list of i2c_board_info which
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the i2c-ocores driver will add to the bus upon creation.
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E.G. something like:
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@ -36,9 +38,24 @@ static struct resource ocores_resources[] = {
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},
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};
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/* optional board info */
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struct i2c_board_info ocores_i2c_board_info[] = {
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{
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I2C_BOARD_INFO("tsc2003", 0x48),
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.platform_data = &tsc2003_platform_data,
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.irq = TSC_IRQ
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},
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{
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I2C_BOARD_INFO("adv7180", 0x42 >> 1),
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.irq = ADV_IRQ
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}
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};
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static struct ocores_i2c_platform_data myi2c_data = {
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.regstep = 2, /* two bytes between registers */
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.clock_khz = 50000, /* input clock of 50MHz */
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.devices = ocores_i2c_board_info, /* optional table of devices */
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.num_devices = ARRAY_SIZE(ocores_i2c_board_info), /* table size */
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};
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static struct platform_device myi2c = {
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@ -298,7 +298,7 @@ config I2C_BLACKFIN_TWI
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config I2C_BLACKFIN_TWI_CLK_KHZ
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int "Blackfin TWI I2C clock (kHz)"
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depends on I2C_BLACKFIN_TWI
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range 10 400
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range 21 400
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default 50
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help
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The unit of the TWI clock is kHz.
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@ -104,9 +104,14 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | STOP);
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else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg+1 < iface->msg_num)
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | RSTART);
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iface->cur_msg + 1 < iface->msg_num) {
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if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | RSTART | MDIR);
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else
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) | RSTART) & ~MDIR);
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}
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SSYNC();
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/* Clear status */
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write_INT_STAT(iface, XMTSERV);
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@ -134,9 +139,13 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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read_MASTER_CTL(iface) | STOP);
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SSYNC();
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} else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg+1 < iface->msg_num) {
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | RSTART);
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iface->cur_msg + 1 < iface->msg_num) {
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if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | RSTART | MDIR);
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else
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) | RSTART) & ~MDIR);
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SSYNC();
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}
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/* Clear interrupt source */
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@ -196,8 +205,6 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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/* remove restart bit and enable master receive */
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) & ~RSTART);
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | MEN | MDIR);
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SSYNC();
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} else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg+1 < iface->msg_num) {
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@ -222,18 +229,19 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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}
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if (iface->pmsg[iface->cur_msg].len <= 255)
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write_MASTER_CTL(iface,
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iface->pmsg[iface->cur_msg].len << 6);
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) &
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(~(0xff << 6))) |
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(iface->pmsg[iface->cur_msg].len << 6));
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else {
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write_MASTER_CTL(iface, 0xff << 6);
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) |
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(0xff << 6)));
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iface->manual_stop = 1;
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}
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/* remove restart bit and enable master receive */
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) & ~RSTART);
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write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
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MEN | ((iface->read_write == I2C_SMBUS_READ) ?
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MDIR : 0));
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SSYNC();
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} else {
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iface->result = 1;
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@ -441,6 +449,16 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
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}
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iface->transPtr = data->block;
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break;
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case I2C_SMBUS_I2C_BLOCK_DATA:
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if (read_write == I2C_SMBUS_READ) {
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iface->readNum = data->block[0];
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iface->cur_mode = TWI_I2C_MODE_COMBINED;
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} else {
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iface->writeNum = data->block[0];
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iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
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}
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iface->transPtr = (u8 *)&data->block[1];
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break;
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default:
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return -1;
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}
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@ -564,7 +582,7 @@ static u32 bfin_twi_functionality(struct i2c_adapter *adap)
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return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
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I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
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I2C_FUNC_I2C;
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I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
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}
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static struct i2c_algorithm bfin_twi_algorithm = {
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@ -614,6 +632,7 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
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struct i2c_adapter *p_adap;
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struct resource *res;
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int rc;
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unsigned int clkhilow;
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iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
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if (!iface) {
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@ -675,10 +694,14 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
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/* Set TWI internal clock as 10MHz */
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write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
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/*
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* We will not end up with a CLKDIV=0 because no one will specify
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* 20kHz SCL or less in Kconfig now. (5 * 1024 / 20 = 0x100)
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*/
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clkhilow = 5 * 1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ;
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/* Set Twi interface clock as specified */
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write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
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<< 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
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& 0xFF));
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write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
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/* Enable TWI */
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write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
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@ -216,6 +216,7 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
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struct ocores_i2c_platform_data *pdata;
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struct resource *res, *res2;
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int ret;
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int i;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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@ -271,6 +272,10 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
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goto add_adapter_failed;
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}
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/* add in known devices to the bus */
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for (i = 0; i < pdata->num_devices; i++)
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i2c_new_device(&i2c->adap, pdata->devices + i);
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return 0;
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add_adapter_failed:
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@ -333,8 +333,18 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
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if (cpu_is_omap2430() || cpu_is_omap34xx()) {
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/* HSI2C controller internal clk rate should be 19.2 Mhz */
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internal_clk = 19200;
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/*
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* HSI2C controller internal clk rate should be 19.2 Mhz for
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* HS and for all modes on 2430. On 34xx we can use lower rate
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* to get longer filter period for better noise suppression.
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* The filter is iclk (fclk for HS) period.
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*/
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if (dev->speed > 400 || cpu_is_omap_2430())
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internal_clk = 19200;
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else if (dev->speed > 100)
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internal_clk = 9600;
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else
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internal_clk = 4000;
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fclk_rate = clk_get_rate(dev->fclk) / 1000;
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/* Compute prescaler divisor */
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/* If configured for High Speed */
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if (dev->speed > 400) {
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unsigned long scl;
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/* For first phase of HS mode */
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fsscll = internal_clk / (400 * 2) - 6;
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fssclh = internal_clk / (400 * 2) - 6;
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scl = internal_clk / 400;
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fsscll = scl - (scl / 3) - 7;
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fssclh = (scl / 3) - 5;
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/* For second phase of HS mode */
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hsscll = fclk_rate / (dev->speed * 2) - 6;
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hssclh = fclk_rate / (dev->speed * 2) - 6;
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scl = fclk_rate / dev->speed;
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hsscll = scl - (scl / 3) - 7;
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hssclh = (scl / 3) - 5;
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} else if (dev->speed > 100) {
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unsigned long scl;
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/* Fast mode */
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scl = internal_clk / dev->speed;
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fsscll = scl - (scl / 3) - 7;
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fssclh = (scl / 3) - 5;
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} else {
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/* To handle F/S modes */
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fsscll = internal_clk / (dev->speed * 2) - 6;
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fssclh = internal_clk / (dev->speed * 2) - 6;
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/* Standard mode */
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fsscll = internal_clk / (dev->speed * 2) - 7;
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fssclh = internal_clk / (dev->speed * 2) - 5;
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}
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scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
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sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
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@ -51,6 +51,11 @@ enum s3c24xx_i2c_state {
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STATE_STOP
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};
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enum s3c24xx_i2c_type {
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TYPE_S3C2410,
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TYPE_S3C2440,
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};
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struct s3c24xx_i2c {
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spinlock_t lock;
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wait_queue_head_t wait;
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@ -88,8 +93,10 @@ struct s3c24xx_i2c {
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static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
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{
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struct platform_device *pdev = to_platform_device(i2c->dev);
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enum s3c24xx_i2c_type type;
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return !strcmp(pdev->name, "s3c2440-i2c");
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type = platform_get_device_id(pdev)->driver_data;
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return type == TYPE_S3C2440;
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}
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/* s3c24xx_i2c_master_complete
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@ -969,52 +976,41 @@ static int s3c24xx_i2c_resume(struct platform_device *dev)
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/* device driver for platform bus bits */
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static struct platform_driver s3c2410_i2c_driver = {
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.probe = s3c24xx_i2c_probe,
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.remove = s3c24xx_i2c_remove,
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.suspend_late = s3c24xx_i2c_suspend_late,
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.resume = s3c24xx_i2c_resume,
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.driver = {
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.owner = THIS_MODULE,
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.name = "s3c2410-i2c",
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},
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static struct platform_device_id s3c24xx_driver_ids[] = {
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{
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.name = "s3c2410-i2c",
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.driver_data = TYPE_S3C2410,
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}, {
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.name = "s3c2440-i2c",
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.driver_data = TYPE_S3C2440,
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}, { },
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};
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MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
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static struct platform_driver s3c2440_i2c_driver = {
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static struct platform_driver s3c24xx_i2c_driver = {
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.probe = s3c24xx_i2c_probe,
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.remove = s3c24xx_i2c_remove,
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.suspend_late = s3c24xx_i2c_suspend_late,
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.resume = s3c24xx_i2c_resume,
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.id_table = s3c24xx_driver_ids,
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.driver = {
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.owner = THIS_MODULE,
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.name = "s3c2440-i2c",
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.name = "s3c-i2c",
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},
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};
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static int __init i2c_adap_s3c_init(void)
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{
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int ret;
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ret = platform_driver_register(&s3c2410_i2c_driver);
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if (ret == 0) {
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ret = platform_driver_register(&s3c2440_i2c_driver);
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if (ret)
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platform_driver_unregister(&s3c2410_i2c_driver);
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}
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return ret;
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return platform_driver_register(&s3c24xx_i2c_driver);
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}
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subsys_initcall(i2c_adap_s3c_init);
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static void __exit i2c_adap_s3c_exit(void)
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{
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platform_driver_unregister(&s3c2410_i2c_driver);
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platform_driver_unregister(&s3c2440_i2c_driver);
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platform_driver_unregister(&s3c24xx_i2c_driver);
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}
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module_exit(i2c_adap_s3c_exit);
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MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
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MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:s3c2410-i2c");
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MODULE_ALIAS("platform:s3c2440-i2c");
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@ -14,6 +14,8 @@
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struct ocores_i2c_platform_data {
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u32 regstep; /* distance between registers */
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u32 clock_khz; /* input clock in kHz */
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u8 num_devices; /* number of devices in the devices list */
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struct i2c_board_info const *devices; /* devices connected to the bus */
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};
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#endif /* _LINUX_I2C_OCORES_H */
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