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Code Issues Releases Wiki Activity

Merge branches 'clk-debugfs', 'clk-spreadtrum', 'clk-sifive', 'clk-counted' and 'clk-qcom' into clk-next

Browse source 
- Add consumer info to clk debugfs
 - Fix various clk drivers that have clk_hw_onecell_data not at the end
   of an allocation

* clk-debugfs:
  clk: Allow phase adjustment from debugfs
  clk: Show active consumers of clocks in debugfs

* clk-spreadtrum:
  clk: sprd: Composite driver support offset config

* clk-sifive:
  clk: sifive: Allow building the driver as a module
  clk: analogbits: Allow building the library as a module

* clk-counted:
  clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data
  clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data
  clk: visconti: Add bounds-checking coverage for struct visconti_pll_provider
  clk: visconti: Fix undefined behavior bug in struct visconti_pll_provider

* clk-qcom: (36 commits)
  clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
  clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
  clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
  clk: qcom: gcc-ipq6018: add QUP6 I2C clock
  clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll
  clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config
  clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll
  clk: qcom: clk-alpha-pll: introduce stromer plus ops
  clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM
  clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configure
  clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure
  clk: qcom: Replace of_device.h with explicit includes
  clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect
  clk: qcom: cbf-msm8996: Convert to platform remove callback returning void
  clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src
  clk: qcom: Add GCC driver support for SM4450
  dt-bindings: clock: qcom: Add GCC clocks for SM4450
  ...
This commit is contained in:
Stephen Boyd 2023-10-30 14:10:51 -07:00
commit d33050aec3
46 changed files with 7364 additions and 366 deletions
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3
Documentation/devicetree/bindings/clock/qcom,hfpll.txt
View file

@ -12,6 +12,9 @@ PROPERTIES
"qcom,hfpll-apq8064", "qcom,hfpll"
"qcom,hfpll-msm8974", "qcom,hfpll"
"qcom,hfpll-msm8960", "qcom,hfpll"
"qcom,msm8976-hfpll-a53", "qcom,hfpll"
"qcom,msm8976-hfpll-a72", "qcom,hfpll"
"qcom,msm8976-hfpll-cci", "qcom,hfpll"
- reg:
Usage: required

1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View file

@ -28,6 +28,7 @@ properties:
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sdx75-rpmh-clk
- qcom,sm4450-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk

55
Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml Normal file
View file

@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h
properties:
compatible:
const: qcom,sm4450-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm4450-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&ufs_mem_phy 0>, <&ufs_mem_phy 1>,
<&ufs_mem_phy 2>, <&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

8
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View file

@ -13,11 +13,15 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h
See also::
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
properties:
compatible:
const: qcom,sm8450-camcc
enum:
- qcom,sm8450-camcc
- qcom,sm8550-camcc
clocks:
items:

2
drivers/clk/analogbits/Kconfig
View file

@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
config CLK_ANALOGBITS_WRPLL_CLN28HPC
bool
tristate

8
drivers/clk/analogbits/wrpll-cln28hpc.c
View file

@ -28,6 +28,7 @@
#include <linux/math64.h>
#include <linux/math.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
@ -312,6 +313,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
return 0;
}
EXPORT_SYMBOL_GPL(wrpll_configure_for_rate);
/**
* wrpll_calc_output_rate() - calculate the PLL's target output rate
@ -349,6 +351,7 @@ unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
return n;
}
EXPORT_SYMBOL_GPL(wrpll_calc_output_rate);
/**
* wrpll_calc_max_lock_us() - return the time for the PLL to lock
@ -366,3 +369,8 @@ unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c)
{
return MAX_LOCK_US;
}
EXPORT_SYMBOL_GPL(wrpll_calc_max_lock_us);
MODULE_AUTHOR("Paul Walmsley <paul.walmsley@sifive.com>");
MODULE_DESCRIPTION("Analog Bits Wide-Range PLL library");
MODULE_LICENSE("GPL");

65
drivers/clk/clk.c
View file

@ -3188,28 +3188,41 @@ static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
int level)
{
int phase;
struct clk *clk_user;
int multi_node = 0;
seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu ",
seq_printf(s, "%*s%-*s %-7d %-8d %-8d %-11lu %-10lu ",
level * 3 + 1, "",
30 - level * 3, c->name,
35 - level * 3, c->name,
c->enable_count, c->prepare_count, c->protect_count,
clk_core_get_rate_recalc(c),
clk_core_get_accuracy_recalc(c));
phase = clk_core_get_phase(c);
if (phase >= 0)
seq_printf(s, "%5d", phase);
seq_printf(s, "%-5d", phase);
else
seq_puts(s, "-----");
seq_printf(s, " %6d", clk_core_get_scaled_duty_cycle(c, 100000));
seq_printf(s, " %-6d", clk_core_get_scaled_duty_cycle(c, 100000));
if (c->ops->is_enabled)
seq_printf(s, " %9c\n", clk_core_is_enabled(c) ? 'Y' : 'N');
seq_printf(s, " %5c ", clk_core_is_enabled(c) ? 'Y' : 'N');
else if (!c->ops->enable)
seq_printf(s, " %9c\n", 'Y');
seq_printf(s, " %5c ", 'Y');
else
seq_printf(s, " %9c\n", '?');
seq_printf(s, " %5c ", '?');
hlist_for_each_entry(clk_user, &c->clks, clks_node) {
seq_printf(s, "%*s%-*s %-25s\n",
level * 3 + 2 + 105 * multi_node, "",
30,
clk_user->dev_id ? clk_user->dev_id : "deviceless",
clk_user->con_id ? clk_user->con_id : "no_connection_id");
multi_node = 1;
}
}
static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
@ -3230,9 +3243,10 @@ static int clk_summary_show(struct seq_file *s, void *data)
struct clk_core *c;
struct hlist_head **lists = s->private;
seq_puts(s, " enable prepare protect duty hardware\n");
seq_puts(s, " clock count count count rate accuracy phase cycle enable\n");
seq_puts(s, "-------------------------------------------------------------------------------------------------------\n");
seq_puts(s, " enable prepare protect duty hardware connection\n");
seq_puts(s, " clock count count count rate accuracy phase cycle enable consumer id\n");
seq_puts(s, "---------------------------------------------------------------------------------------------------------------------------------------------\n");
clk_prepare_lock();
@ -3329,6 +3343,21 @@ static int clk_rate_set(void *data, u64 val)
#define clk_rate_mode 0644
static int clk_phase_set(void *data, u64 val)
{
struct clk_core *core = data;
int degrees = do_div(val, 360);
int ret;
clk_prepare_lock();
ret = clk_core_set_phase_nolock(core, degrees);
clk_prepare_unlock();
return ret;
}
#define clk_phase_mode 0644
static int clk_prepare_enable_set(void *data, u64 val)
{
struct clk_core *core = data;
@ -3356,6 +3385,9 @@ DEFINE_DEBUGFS_ATTRIBUTE(clk_prepare_enable_fops, clk_prepare_enable_get,
#else
#define clk_rate_set NULL
#define clk_rate_mode 0444
#define clk_phase_set NULL
#define clk_phase_mode 0644
#endif
static int clk_rate_get(void *data, u64 *val)
@ -3371,6 +3403,16 @@ static int clk_rate_get(void *data, u64 *val)
DEFINE_DEBUGFS_ATTRIBUTE(clk_rate_fops, clk_rate_get, clk_rate_set, "%llu\n");
static int clk_phase_get(void *data, u64 *val)
{
struct clk_core *core = data;
*val = core->phase;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(clk_phase_fops, clk_phase_get, clk_phase_set, "%llu\n");
static const struct {
unsigned long flag;
const char *name;
@ -3564,7 +3606,8 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
debugfs_create_file("clk_min_rate", 0444, root, core, &clk_min_rate_fops);
debugfs_create_file("clk_max_rate", 0444, root, core, &clk_max_rate_fops);
debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
debugfs_create_u32("clk_phase", 0444, root, &core->phase);
debugfs_create_file("clk_phase", clk_phase_mode, root, core,
&clk_phase_fops);
debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);
debugfs_create_u32("clk_prepare_count", 0444, root, &core->prepare_count);
debugfs_create_u32("clk_enable_count", 0444, root, &core->enable_count);

17
drivers/clk/qcom/Kconfig
View file

@ -131,6 +131,7 @@ config IPQ_APSS_6018
tristate "IPQ APSS Clock Controller"
select IPQ_APSS_PLL
depends on QCOM_APCS_IPC || COMPILE_TEST
depends on QCOM_SMEM
help
Support for APSS clock controller on IPQ platforms. The
APSS clock controller manages the Mux and enable block that feeds the
@ -764,6 +765,13 @@ config SM_CAMCC_8450
Support for the camera clock controller on SM8450 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_CAMCC_8550
tristate "SM8550 Camera Clock Controller"
select SM_GCC_8550
help
Support for the camera clock controller on SM8550 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_DISPCC_6115
tristate "SM6115 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -834,6 +842,15 @@ config SM_DISPCC_8550
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_GCC_4450
tristate "SM4450 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on SM4450 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, SD/UFS, PCIe, etc.
config SM_GCC_6115
tristate "SM6115 and SM4250 Global Clock Controller"
depends on ARM64 || COMPILE_TEST

2
drivers/clk/qcom/Makefile
View file

@ -102,6 +102,7 @@ obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
@ -109,6 +110,7 @@ obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o
obj-$(CONFIG_SM_GCC_4450) += gcc-sm4450.o
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o

4
drivers/clk/qcom/apss-ipq-pll.c
View file

@ -68,13 +68,13 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_stromer_ops,
.ops = &clk_alpha_pll_stromer_plus_ops,
},
},
};
static const struct alpha_pll_config ipq5332_pll_config = {
.l = 0x3e,
.l = 0x2d,
.config_ctl_val = 0x4001075b,
.config_ctl_hi_val = 0x304,
.main_output_mask = BIT(0),

61
drivers/clk/qcom/apss-ipq6018.c
View file

@ -9,8 +9,11 @@
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/soc/qcom/smem.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/arm/qcom,ids.h>
#include "common.h"
#include "clk-regmap.h"
@ -20,16 +23,19 @@
enum {
P_XO,
P_GPLL0,
P_APSS_PLL_EARLY,
};
static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
{ .fw_name = "xo" },
{ .fw_name = "gpll0" },
{ .fw_name = "pll" },
};
static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 4 },
{ P_APSS_PLL_EARLY, 5 },
};
@ -81,15 +87,68 @@ static const struct qcom_cc_desc apss_ipq6018_desc = {
.num_clks = ARRAY_SIZE(apss_ipq6018_clks),
};
static int cpu_clk_notifier_fn(struct notifier_block *nb, unsigned long action,
void *data)
{
struct clk_hw *hw;
u8 index;
int err;
if (action == PRE_RATE_CHANGE)
index = P_GPLL0;
else if (action == POST_RATE_CHANGE || action == ABORT_RATE_CHANGE)
index = P_APSS_PLL_EARLY;
else
return NOTIFY_OK;
hw = &apcs_alias0_clk_src.clkr.hw;
err = clk_rcg2_mux_closest_ops.set_parent(hw, index);
return notifier_from_errno(err);
}
static int apss_ipq6018_probe(struct platform_device *pdev)
{
struct clk_hw *hw = &apcs_alias0_clk_src.clkr.hw;
struct notifier_block *cpu_clk_notifier;
struct regmap *regmap;
u32 soc_id;
int ret;
ret = qcom_smem_get_soc_id(&soc_id);
if (ret)
return ret;
regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!regmap)
return -ENODEV;
return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
ret = qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
if (ret)
return ret;
switch (soc_id) {
/* Only below variants of IPQ53xx support scaling */
case QCOM_ID_IPQ5332:
case QCOM_ID_IPQ5322:
case QCOM_ID_IPQ5300:
cpu_clk_notifier = devm_kzalloc(&pdev->dev,
sizeof(*cpu_clk_notifier),
GFP_KERNEL);
if (!cpu_clk_notifier)
return -ENOMEM;
cpu_clk_notifier->notifier_call = cpu_clk_notifier_fn;
ret = devm_clk_notifier_register(&pdev->dev, hw->clk, cpu_clk_notifier);
if (ret)
return ret;
break;
default:
break;
}
return 0;
}
static struct platform_driver apss_ipq6018_driver = {

3565
drivers/clk/qcom/camcc-sm8550.c Normal file
View file

File diff suppressed because it is too large Load diff

92
drivers/clk/qcom/clk-alpha-pll.c
View file

@ -271,6 +271,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
#define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24
/* ZONDA PLL specific */
#define ZONDA_PLL_OUT_MASK 0xf
@ -2119,6 +2120,34 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
}
EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
u32 lval = config->l;
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
/* Disable PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
/* Set operation mode to STANDBY and de-assert the reset */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);
static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
@ -2479,3 +2508,66 @@ const struct clk_ops clk_alpha_pll_stromer_ops = {
.set_rate = clk_alpha_pll_stromer_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, alpha_width = pll_alpha_width(pll);
int ret, pll_mode;
u64 a;
rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
if (ret)
return ret;
regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
/* Delay of 2 output clock ticks required until output is disabled */
udelay(1);
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
if (alpha_width > ALPHA_BITWIDTH)
a <<= alpha_width - ALPHA_BITWIDTH;
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
a >> ALPHA_BITWIDTH);
regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
/* Wait five micro seconds or more */
udelay(5);
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
PLL_RESET_N);
/* The lock time should be less than 50 micro seconds worst case */
usleep_range(50, 60);
ret = wait_for_pll_enable_lock(pll);
if (ret) {
pr_err("Wait for PLL enable lock failed [%s] %d\n",
clk_hw_get_name(hw), ret);
return ret;
}
if (pll_mode & PLL_OUTCTRL)
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,
PLL_OUTCTRL);
return 0;
}
const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
.prepare = clk_alpha_pll_enable,
.unprepare = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.determine_rate = clk_alpha_pll_stromer_determine_rate,
.set_rate = clk_alpha_pll_stromer_plus_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);

3
drivers/clk/qcom/clk-alpha-pll.h
View file

@ -152,6 +152,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_ops;
extern const struct clk_ops clk_alpha_pll_huayra_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
extern const struct clk_ops clk_alpha_pll_stromer_ops;
extern const struct clk_ops clk_alpha_pll_stromer_plus_ops;
extern const struct clk_ops clk_alpha_pll_fabia_ops;
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
@ -199,6 +200,8 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

12
drivers/clk/qcom/clk-cbf-8996.c
View file

@ -250,13 +250,11 @@ static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct cl
return 0;
}
static int qcom_msm8996_cbf_icc_remove(struct platform_device *pdev)
static void qcom_msm8996_cbf_icc_remove(struct platform_device *pdev)
{
struct icc_provider *provider = platform_get_drvdata(pdev);
icc_clk_unregister(provider);
return 0;
}
#define qcom_msm8996_cbf_icc_sync_state icc_sync_state
#else
@ -266,7 +264,7 @@ static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct c
return 0;
}
#define qcom_msm8996_cbf_icc_remove(pdev) (0)
#define qcom_msm8996_cbf_icc_remove(pdev) { }
#define qcom_msm8996_cbf_icc_sync_state NULL
#endif
@ -340,9 +338,9 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev)
return qcom_msm8996_cbf_icc_register(pdev, &cbf_mux.clkr.hw);
}
static int qcom_msm8996_cbf_remove(struct platform_device *pdev)
static void qcom_msm8996_cbf_remove(struct platform_device *pdev)
{
return qcom_msm8996_cbf_icc_remove(pdev);
qcom_msm8996_cbf_icc_remove(pdev);
}
static const struct of_device_id qcom_msm8996_cbf_match_table[] = {
@ -354,7 +352,7 @@ MODULE_DEVICE_TABLE(of, qcom_msm8996_cbf_match_table);
static struct platform_driver qcom_msm8996_cbf_driver = {
.probe = qcom_msm8996_cbf_probe,
.remove = qcom_msm8996_cbf_remove,
.remove_new = qcom_msm8996_cbf_remove,
.driver = {
.name = "qcom-msm8996-cbf",
.of_match_table = qcom_msm8996_cbf_match_table,

4
drivers/clk/qcom/clk-hfpll.c
View file

@ -44,6 +44,10 @@ static void __clk_hfpll_init_once(struct clk_hw *hw)
regmap_write(regmap, hd->user_reg, regval);
}
/* Write L_VAL from conf if it exist */
if (hd->l_val)
regmap_write(regmap, hd->l_reg, hd->l_val);
if (hd->droop_reg)
regmap_write(regmap, hd->droop_reg, hd->droop_val);

1
drivers/clk/qcom/clk-hfpll.h
View file

@ -18,6 +18,7 @@ struct hfpll_data {
u32 status_reg;
u8 lock_bit;
u32 l_val;
u32 droop_val;
u32 config_val;
u32 user_val;

14
drivers/clk/qcom/clk-rcg2.c
View file

@ -158,17 +158,11 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
static unsigned long
calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
{
if (hid_div) {
rate *= 2;
rate /= hid_div + 1;
}
if (hid_div)
rate = mult_frac(rate, 2, hid_div + 1);
if (mode) {
u64 tmp = rate;
tmp *= m;
do_div(tmp, n);
rate = tmp;
}
if (mode)
rate = mult_frac(rate, m, n);
return rate;
}

21
drivers/clk/qcom/clk-rpmh.c
View file

@ -350,6 +350,7 @@ DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a4, "lnbclka3", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4);
@ -717,6 +718,25 @@ static const struct clk_rpmh_desc clk_rpmh_sdx75 = {
.num_clks = ARRAY_SIZE(sdx75_rpmh_clocks),
};
static struct clk_hw *sm4450_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a4.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a4_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm4450 = {
.clks = sm4450_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm4450_rpmh_clocks),
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@ -810,6 +830,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
{ .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
{ .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75},
{ .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450},
{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},

16
drivers/clk/qcom/clk-smd-rpm.c
View file

@ -574,6 +574,16 @@ static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = {
&clk_smd_rpm_bus_2_snoc_clk,
};
static const struct clk_smd_rpm *qcm2290_icc_clks[] = {
&clk_smd_rpm_bimc_clk,
&clk_smd_rpm_bus_1_cnoc_clk,
&clk_smd_rpm_mmnrt_clk,
&clk_smd_rpm_mmrt_clk,
&clk_smd_rpm_qup_clk,
&clk_smd_rpm_bus_2_snoc_clk,
&clk_smd_rpm_cpuss_gnoc_clk,
};
static struct clk_smd_rpm *msm8909_clks[] = {
[RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
[RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
@ -1189,15 +1199,13 @@ static struct clk_smd_rpm *qcm2290_clks[] = {
[RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk,
[RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,
[RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,
[RPM_SMD_CPUSS_GNOC_CLK] = &clk_smd_rpm_cpuss_gnoc_clk,
[RPM_SMD_CPUSS_GNOC_A_CLK] = &clk_smd_rpm_cpuss_gnoc_a_clk,
};
static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
.clks = qcm2290_clks,
.num_clks = ARRAY_SIZE(qcm2290_clks),
.icc_clks = sm_qnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
.icc_clks = qcm2290_icc_clks,
.num_icc_clks = ARRAY_SIZE(qcm2290_icc_clks)
};
static const struct of_device_id rpm_smd_clk_match_table[] = {

6
drivers/clk/qcom/gcc-ipq5018.c
View file

@ -3,8 +3,9 @@
* Copyright (c) 2023, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
@ -128,7 +129,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -143,7 +143,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -158,7 +157,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};

4
drivers/clk/qcom/gcc-ipq5332.c
View file

@ -71,7 +71,6 @@ static struct clk_fixed_factor gpll0_div2 = {
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -85,7 +84,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -114,7 +112,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
&gpll2_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -154,7 +151,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
&gpll4_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};

27
drivers/clk/qcom/gcc-ipq6018.c
View file

@ -72,7 +72,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -86,7 +85,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -161,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll6 = {
&gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -192,7 +189,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
&gpll4_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -243,7 +239,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
&gpll2_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -274,7 +269,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = {
&nss_crypto_pll_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -2125,6 +2119,26 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x07010,
.clkr = {
.enable_reg = 0x07010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
/*
* RPM uses QUP6 I2C to communicate with the external
* PMIC so it must not be disabled.
*/
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x0700c,
.clkr = {
@ -4281,6 +4295,7 @@ static struct clk_regmap *gcc_ipq6018_clks[] = {
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,

6
drivers/clk/qcom/gcc-ipq8074.c
View file

@ -75,7 +75,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -121,7 +120,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
&gpll2_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -154,7 +152,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
&gpll4_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -188,7 +185,6 @@ static struct clk_alpha_pll_postdiv gpll6 = {
&gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -201,7 +197,6 @@ static struct clk_fixed_factor gpll6_out_main_div2 = {
&gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -266,7 +261,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = {
&nss_crypto_pll_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};

4
drivers/clk/qcom/gcc-ipq9574.c
View file

@ -87,7 +87,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
&gpll0_main.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
@ -102,7 +101,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
&gpll0_main.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
@ -132,7 +130,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
&gpll4_main.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
@ -162,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
&gpll2_main.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};

237
drivers/clk/qcom/gcc-msm8996.c
View file

@ -244,71 +244,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
{ .hw = &gpll0_early_div.hw }
};
static const struct freq_tbl ftbl_system_noc_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 system_noc_clk_src = {
.cmd_rcgr = 0x0401c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
.freq_tbl = ftbl_system_noc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_config_noc_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 config_noc_clk_src = {
.cmd_rcgr = 0x0500c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_config_noc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "config_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 periph_noc_clk_src = {
.cmd_rcgr = 0x06014,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_periph_noc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "periph_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(120000000, P_GPLL0, 5, 0, 0),
@ -1297,11 +1232,7 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_noc_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.flags = CLK_IGNORE_UNUSED,
.ops = &clk_branch2_ops,
},
},
@ -1464,11 +1395,6 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1498,11 +1424,6 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1549,11 +1470,6 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1583,11 +1499,6 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1617,11 +1528,6 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1635,11 +1541,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1977,11 +1878,6 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2318,11 +2214,6 @@ static struct clk_branch gcc_pdm_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2353,11 +2244,6 @@ static struct clk_branch gcc_prng_ahb_clk = {
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2370,11 +2256,6 @@ static struct clk_branch gcc_tsif_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2422,11 +2303,6 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2520,11 +2396,6 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2537,11 +2408,6 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2554,11 +2420,6 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2606,11 +2467,6 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2623,11 +2479,6 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2640,11 +2491,6 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2692,11 +2538,6 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_slv_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2709,11 +2550,6 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_mstr_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2726,11 +2562,6 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2778,11 +2609,6 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -2829,11 +2655,6 @@ static struct clk_branch gcc_ufs_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -3060,11 +2881,7 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre0_snoc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@ -3077,11 +2894,7 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre0_cnoc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@ -3094,11 +2907,7 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_aggre0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@ -3111,11 +2920,7 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_aggre0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@ -3162,10 +2967,6 @@ static struct clk_branch gcc_dcc_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_dcc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -3178,10 +2979,6 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -3194,11 +2991,6 @@ static struct clk_branch gcc_qspi_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -3347,10 +3139,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -3363,10 +3151,6 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_mnoc_bimc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -3379,10 +3163,6 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_snoc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -3395,10 +3175,6 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -3495,9 +3271,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL4_EARLY] = &gpll4_early.clkr,
[GPLL4] = &gpll4.clkr,
[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,

2898
drivers/clk/qcom/gcc-sm4450.c Normal file
View file

File diff suppressed because it is too large Load diff

2
drivers/clk/qcom/gcc-sm8150.c
View file

@ -774,7 +774,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_floor_ops,
},
};

10
drivers/clk/qcom/gpucc-sm8550.c
View file

@ -39,8 +39,7 @@ static const struct pll_vco lucid_ole_vco[] = {
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
.l = 0x4444000d,
.l = 0x0d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@ -71,8 +70,7 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
};
static const struct alpha_pll_config gpu_cc_pll1_config = {
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
.l = 0x44440016,
.l = 0x16,
.alpha = 0xeaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@ -574,8 +572,8 @@ static int gpu_cc_sm8550_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Keep clocks always enabled:

59
drivers/clk/qcom/hfpll.c
View file

@ -6,6 +6,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
@ -31,8 +32,62 @@ static const struct hfpll_data hdata = {
.max_rate = 2900000000UL,
};
static const struct hfpll_data msm8976_a53 = {
.mode_reg = 0x00,
.l_reg = 0x04,
.m_reg = 0x08,
.n_reg = 0x0c,
.user_reg = 0x10,
.config_reg = 0x14,
.config_val = 0x341600,
.status_reg = 0x1c,
.lock_bit = 16,
.l_val = 0x35,
.user_val = 0x109,
.min_rate = 902400000UL,
.max_rate = 1478400000UL,
};
static const struct hfpll_data msm8976_a72 = {
.mode_reg = 0x00,
.l_reg = 0x04,
.m_reg = 0x08,
.n_reg = 0x0c,
.user_reg = 0x10,
.config_reg = 0x14,
.config_val = 0x4e0405d,
.status_reg = 0x1c,
.lock_bit = 16,
.l_val = 0x3e,
.user_val = 0x100109,
.min_rate = 940800000UL,
.max_rate = 2016000000UL,
};
static const struct hfpll_data msm8976_cci = {
.mode_reg = 0x00,
.l_reg = 0x04,
.m_reg = 0x08,
.n_reg = 0x0c,
.user_reg = 0x10,
.config_reg = 0x14,
.config_val = 0x141400,
.status_reg = 0x1c,
.lock_bit = 16,
.l_val = 0x20,
.user_val = 0x100109,
.min_rate = 556800000UL,
.max_rate = 902400000UL,
};
static const struct of_device_id qcom_hfpll_match_table[] = {
{ .compatible = "qcom,hfpll" },
{ .compatible = "qcom,hfpll", .data = &hdata },
{ .compatible = "qcom,msm8976-hfpll-a53", .data = &msm8976_a53 },
{ .compatible = "qcom,msm8976-hfpll-a72", .data = &msm8976_a72 },
{ .compatible = "qcom,msm8976-hfpll-cci", .data = &msm8976_cci },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
@ -83,7 +138,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
init.parent_data = &pdata;
h->d = &hdata;
h->d = of_device_get_match_data(&pdev->dev);
h->clkr.hw.init = &init;
spin_lock_init(&h->lock);

18
drivers/clk/qcom/mmcc-msm8974.c
View file

@ -2170,22 +2170,6 @@ static struct clk_branch mmss_s0_axi_clk = {
},
};
static struct clk_branch ocmemcx_ahb_clk = {
.halt_reg = 0x405c,
.clkr = {
.enable_reg = 0x405c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ocmemcx_ocmemnoc_clk = {
.halt_reg = 0x4058,
.clkr = {
@ -2503,7 +2487,6 @@ static struct clk_regmap *mmcc_msm8226_clocks[] = {
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
@ -2660,7 +2643,6 @@ static struct clk_regmap *mmcc_msm8974_clocks[] = {
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
[OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,

7
drivers/clk/qcom/mmcc-msm8998.c
View file

@ -2439,6 +2439,7 @@ static struct clk_branch fd_ahb_clk = {
static struct clk_branch mnoc_ahb_clk = {
.halt_reg = 0x5024,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x5024,
.enable_mask = BIT(0),
@ -2454,6 +2455,7 @@ static struct clk_branch mnoc_ahb_clk = {
static struct clk_branch bimc_smmu_ahb_clk = {
.halt_reg = 0xe004,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xe004,
.hwcg_bit = 1,
.clkr = {
@ -2471,6 +2473,7 @@ static struct clk_branch bimc_smmu_ahb_clk = {
static struct clk_branch bimc_smmu_axi_clk = {
.halt_reg = 0xe008,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xe008,
.hwcg_bit = 1,
.clkr = {
@ -2607,11 +2610,13 @@ static struct gdsc camss_cpp_gdsc = {
static struct gdsc bimc_smmu_gdsc = {
.gdscr = 0xe020,
.gds_hw_ctrl = 0xe024,
.cxcs = (unsigned int []){ 0xe008 },
.cxc_count = 1,
.pd = {
.name = "bimc_smmu",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | ALWAYS_ON,
.flags = VOTABLE,
};
static struct clk_regmap *mmcc_msm8998_clocks[] = {

10
drivers/clk/qcom/videocc-sm8550.c
View file

@ -36,8 +36,7 @@ static const struct pll_vco lucid_ole_vco[] = {
};
static const struct alpha_pll_config video_cc_pll0_config = {
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
.l = 0x44440025,
.l = 0x25,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@ -68,8 +67,7 @@ static struct clk_alpha_pll video_cc_pll0 = {
};
static const struct alpha_pll_config video_cc_pll1_config = {
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
.l = 0x44440036,
.l = 0x36,
.alpha = 0xb000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@ -427,8 +425,8 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
return PTR_ERR(regmap);
}
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
/*
* Keep clocks always enabled:

2
drivers/clk/sifive/Kconfig
View file

@ -10,7 +10,7 @@ menuconfig CLK_SIFIVE
if CLK_SIFIVE
config CLK_SIFIVE_PRCI
bool "PRCI driver for SiFive SoCs"
tristate "PRCI driver for SiFive SoCs"
default ARCH_SIFIVE
select RESET_CONTROLLER
select RESET_SIMPLE

10
drivers/clk/sifive/sifive-prci.c
View file

@ -7,6 +7,7 @@
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include "sifive-prci.h"
#include "fu540-prci.h"
@ -618,9 +619,8 @@ static struct platform_driver sifive_prci_driver = {
},
.probe = sifive_prci_probe,
};
module_platform_driver(sifive_prci_driver);
static int __init sifive_prci_init(void)
{
return platform_driver_register(&sifive_prci_driver);
}
core_initcall(sifive_prci_init);
MODULE_AUTHOR("Paul Walmsley <paul.walmsley@sifive.com>");
MODULE_DESCRIPTION("SiFive Power Reset Clock Interface (PRCI) driver");
MODULE_LICENSE("GPL");

12
drivers/clk/socfpga/clk-agilex.c
View file

@ -471,12 +471,12 @@ static int agilex_clkmgr_init(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
clk_data->clk_data.num = num_clks;
clk_data->base = base;
for (i = 0; i < num_clks; i++)
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
clk_data->base = base;
clk_data->clk_data.num = num_clks;
agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
agilex_clk_register_c_perip(agilex_main_perip_c_clks,
@ -511,12 +511,12 @@ static int n5x_clkmgr_init(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
for (i = 0; i < num_clks; i++)
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
clk_data->base = base;
clk_data->clk_data.num = num_clks;
for (i = 0; i < num_clks; i++)
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
n5x_clk_register_c_perip(n5x_main_perip_c_clks,

6
drivers/clk/socfpga/clk-s10.c
View file

@ -402,12 +402,12 @@ static int s10_clkmgr_init(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
for (i = 0; i < num_clks; i++)
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
clk_data->base = base;
clk_data->clk_data.num = num_clks;
for (i = 0; i < num_clks; i++)
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
s10_clk_register_c_perip(s10_main_perip_c_clks,

4
drivers/clk/socfpga/stratix10-clk.h
View file

@ -7,8 +7,10 @@
#define __STRATIX10_CLK_H
struct stratix10_clock_data {
struct clk_hw_onecell_data clk_data;
void __iomem *base;
/* Must be last */
struct clk_hw_onecell_data clk_data;
};
struct stratix10_pll_clock {

36
drivers/clk/sprd/composite.h
View file

@ -19,24 +19,24 @@ struct sprd_comp {
};
#define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
_mshift, _mwidth, _dshift, _dwidth, \
_flags, _fn) \
_mshift, _mwidth, _doffset, _dshift, \
_dwidth, _flags, _fn) \
struct sprd_comp _struct = { \
.mux = _SPRD_MUX_CLK(_mshift, _mwidth, _table), \
.div = _SPRD_DIV_CLK(_dshift, _dwidth), \
.div = _SPRD_DIV_CLK(_doffset, _dshift, _dwidth), \
.common = { \
.regmap = NULL, \
.reg = _reg, \
.hw.init = _fn(_name, _parent, \
&sprd_comp_ops, _flags), \
} \
} \
}
#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
_mshift, _mwidth, _dshift, _dwidth, _flags) \
SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
_mshift, _mwidth, _dshift, _dwidth, \
_flags, CLK_HW_INIT_PARENTS)
_mshift, _mwidth, 0x0, _dshift, \
_dwidth, _flags, CLK_HW_INIT_PARENTS)
#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
_mwidth, _dshift, _dwidth, _flags) \
@ -47,15 +47,33 @@ struct sprd_comp {
_mshift, _mwidth, _dshift, \
_dwidth, _flags) \
SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
_mshift, _mwidth, _dshift, _dwidth, \
_flags, CLK_HW_INIT_PARENTS_DATA)
_mshift, _mwidth, 0x0, _dshift, \
_dwidth, _flags, \
CLK_HW_INIT_PARENTS_DATA)
#define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \
_mwidth, _dshift, _dwidth, _flags) \
SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
_mshift, _mwidth, _dshift, _dwidth, \
_flags)
#define SPRD_COMP_CLK_DATA_TABLE_OFFSET(_struct, _name, _parent, _reg, \
_table, _mshift, _mwidth, \
_doffset, _dshift, _dwidth, \
_flags) \
SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
_mshift, _mwidth, _doffset, _dshift, \
_dwidth, _flags, \
CLK_HW_INIT_PARENTS_DATA)
#define SPRD_COMP_CLK_DATA_OFFSET(_struct, _name, _parent, _reg, \
_mshift, _mwidth, _doffset, _dshift, \
_dwidth, _flags) \
SPRD_COMP_CLK_DATA_TABLE_OFFSET(_struct, _name, _parent, _reg, \
NULL, _mshift, _mwidth, \
_doffset, _dshift, _dwidth, \
_flags)
static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw)
{
struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);

6
drivers/clk/sprd/div.c
View file

@ -25,7 +25,7 @@ unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
unsigned long val;
unsigned int reg;
regmap_read(common->regmap, common->reg, &reg);
regmap_read(common->regmap, common->reg + div->offset, &reg);
val = reg >> div->shift;
val &= (1 << div->width) - 1;
@ -53,10 +53,10 @@ int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
val = divider_get_val(rate, parent_rate, NULL,
div->width, 0);
regmap_read(common->regmap, common->reg, &reg);
regmap_read(common->regmap, common->reg + div->offset, &reg);
reg &= ~GENMASK(div->width + div->shift - 1, div->shift);
regmap_write(common->regmap, common->reg,
regmap_write(common->regmap, common->reg + div->offset,
reg | (val << div->shift));
return 0;

17
drivers/clk/sprd/div.h
View file

@ -20,12 +20,14 @@
* classes.
*/
struct sprd_div_internal {
s32 offset;
u8 shift;
u8 width;
};
#define _SPRD_DIV_CLK(_shift, _width) \
#define _SPRD_DIV_CLK(_offset, _shift, _width) \
{ \
.offset = _offset, \
.shift = _shift, \
.width = _width, \
}
@ -35,10 +37,10 @@ struct sprd_div {
struct sprd_clk_common common;
};
#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \
_shift, _width, _flags, _fn) \
struct sprd_div _struct = { \
.div = _SPRD_DIV_CLK(_shift, _width), \
.div = _SPRD_DIV_CLK(_offset, _shift, _width), \
.common = { \
.regmap = NULL, \
.reg = _reg, \
@ -49,12 +51,17 @@ struct sprd_div {
#define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
_shift, _width, _flags) \
SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
_shift, _width, _flags, CLK_HW_INIT)
#define SPRD_DIV_CLK_FW_NAME(_struct, _name, _parent, _reg, \
_shift, _width, _flags) \
SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
_shift, _width, _flags, CLK_HW_INIT_FW_NAME)
#define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \
_shift, _width, _flags) \
SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
_shift, _width, _flags, CLK_HW_INIT_HW)
static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)

6
drivers/clk/visconti/pll.c
View file

@ -329,12 +329,12 @@ struct visconti_pll_provider * __init visconti_init_pll(struct device_node *np,
if (!ctx)
return ERR_PTR(-ENOMEM);
for (i = 0; i < nr_plls; ++i)
ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
ctx->node = np;
ctx->reg_base = base;
ctx->clk_data.num = nr_plls;
for (i = 0; i < nr_plls; ++i)
ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
return ctx;
}

4
drivers/clk/visconti/pll.h
View file

@ -15,8 +15,10 @@
struct visconti_pll_provider {
void __iomem *reg_base;
struct clk_hw_onecell_data clk_data;
struct device_node *node;
/* Must be last */
struct clk_hw_onecell_data clk_data;
};
#define VISCONTI_PLL_RATE(_rate, _dacen, _dsmen, \

1
include/dt-bindings/clock/qcom,mmcc-msm8974.h
View file

@ -121,7 +121,6 @@
#define MMSS_MMSSNOC_BTO_AHB_CLK 112
#define MMSS_MMSSNOC_AXI_CLK 113
#define MMSS_S0_AXI_CLK 114
#define OCMEMCX_AHB_CLK 115
#define OCMEMCX_OCMEMNOC_CLK 116
#define OXILI_OCMEMGX_CLK 117
#define OCMEMNOC_CLK 118

197
include/dt-bindings/clock/qcom,sm4450-gcc.h Normal file
View file

@ -0,0 +1,197 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 0
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
#define GCC_BOOT_ROM_AHB_CLK 4
#define GCC_CAMERA_AHB_CLK 5
#define GCC_CAMERA_HF_AXI_CLK 6
#define GCC_CAMERA_SF_AXI_CLK 7
#define GCC_CAMERA_SLEEP_CLK 8
#define GCC_CAMERA_XO_CLK 9
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11
#define GCC_DDRSS_GPU_AXI_CLK 12
#define GCC_DDRSS_PCIE_SF_TBU_CLK 13
#define GCC_DISP_AHB_CLK 14
#define GCC_DISP_HF_AXI_CLK 15
#define GCC_DISP_XO_CLK 16
#define GCC_EUSB3_0_CLKREF_EN 17
#define GCC_GP1_CLK 18
#define GCC_GP1_CLK_SRC 19
#define GCC_GP2_CLK 20
#define GCC_GP2_CLK_SRC 21
#define GCC_GP3_CLK 22
#define GCC_GP3_CLK_SRC 23
#define GCC_GPLL0 24
#define GCC_GPLL0_OUT_EVEN 25
#define GCC_GPLL0_OUT_ODD 26
#define GCC_GPLL1 27
#define GCC_GPLL3 28
#define GCC_GPLL4 29
#define GCC_GPLL9 30
#define GCC_GPLL10 31
#define GCC_GPU_CFG_AHB_CLK 32
#define GCC_GPU_GPLL0_CLK_SRC 33
#define GCC_GPU_GPLL0_DIV_CLK_SRC 34
#define GCC_GPU_MEMNOC_GFX_CLK 35
#define GCC_GPU_SNOC_DVM_GFX_CLK 36
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK 37
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK 38
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK 39
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK 40
#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK 41
#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK 42
#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK 43
#define GCC_HLOS1_VOTE_MMU_TCU_CLK 44
#define GCC_PCIE_0_AUX_CLK 45
#define GCC_PCIE_0_AUX_CLK_SRC 46
#define GCC_PCIE_0_CFG_AHB_CLK 47
#define GCC_PCIE_0_CLKREF_EN 48
#define GCC_PCIE_0_MSTR_AXI_CLK 49
#define GCC_PCIE_0_PHY_RCHNG_CLK 50
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51
#define GCC_PCIE_0_PIPE_CLK 52
#define GCC_PCIE_0_PIPE_CLK_SRC 53
#define GCC_PCIE_0_PIPE_DIV2_CLK 54
#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 55
#define GCC_PCIE_0_SLV_AXI_CLK 56
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
#define GCC_PDM2_CLK 58
#define GCC_PDM2_CLK_SRC 59
#define GCC_PDM_AHB_CLK 60
#define GCC_PDM_XO4_CLK 61
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 62
#define GCC_QMIP_CAMERA_RT_AHB_CLK 63
#define GCC_QMIP_DISP_AHB_CLK 64
#define GCC_QMIP_GPU_AHB_CLK 65
#define GCC_QMIP_PCIE_AHB_CLK 66
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 68
#define GCC_QUPV3_WRAP0_CORE_CLK 69
#define GCC_QUPV3_WRAP0_S0_CLK 70
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 71
#define GCC_QUPV3_WRAP0_S1_CLK 72
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 73
#define GCC_QUPV3_WRAP0_S2_CLK 74
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 75
#define GCC_QUPV3_WRAP0_S3_CLK 76
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 77
#define GCC_QUPV3_WRAP0_S4_CLK 78
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 79
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 80
#define GCC_QUPV3_WRAP1_CORE_CLK 81
#define GCC_QUPV3_WRAP1_S0_CLK 82
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 83
#define GCC_QUPV3_WRAP1_S1_CLK 84
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 85
#define GCC_QUPV3_WRAP1_S2_CLK 86
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 87
#define GCC_QUPV3_WRAP1_S3_CLK 88
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 89
#define GCC_QUPV3_WRAP1_S4_CLK 90
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 91
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 92
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 93
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 94
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 95
#define GCC_SDCC1_AHB_CLK 96
#define GCC_SDCC1_APPS_CLK 97
#define GCC_SDCC1_APPS_CLK_SRC 98
#define GCC_SDCC1_ICE_CORE_CLK 99
#define GCC_SDCC1_ICE_CORE_CLK_SRC 100
#define GCC_SDCC2_AHB_CLK 101
#define GCC_SDCC2_APPS_CLK 102
#define GCC_SDCC2_APPS_CLK_SRC 103
#define GCC_UFS_0_CLKREF_EN 104
#define GCC_UFS_PAD_CLKREF_EN 105
#define GCC_UFS_PHY_AHB_CLK 106
#define GCC_UFS_PHY_AXI_CLK 107
#define GCC_UFS_PHY_AXI_CLK_SRC 108
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 109
#define GCC_UFS_PHY_ICE_CORE_CLK 110
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 111
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 112
#define GCC_UFS_PHY_PHY_AUX_CLK 113
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 114
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 115
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 116
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 117
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 118
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 119
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 120
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 121
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 122
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 123
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 124
#define GCC_USB30_PRIM_MASTER_CLK 125
#define GCC_USB30_PRIM_MASTER_CLK_SRC 126
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 127
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 128
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 129
#define GCC_USB30_PRIM_SLEEP_CLK 130
#define GCC_USB3_0_CLKREF_EN 131
#define GCC_USB3_PRIM_PHY_AUX_CLK 132
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 133
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 134
#define GCC_USB3_PRIM_PHY_PIPE_CLK 135
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 136
#define GCC_VCODEC0_AXI_CLK 137
#define GCC_VENUS_CTL_AXI_CLK 138
#define GCC_VIDEO_AHB_CLK 139
#define GCC_VIDEO_THROTTLE_CORE_CLK 140
#define GCC_VIDEO_VCODEC0_SYS_CLK 141
#define GCC_VIDEO_VENUS_CLK_SRC 142
#define GCC_VIDEO_VENUS_CTL_CLK 143
#define GCC_VIDEO_XO_CLK 144
/* GCC power domains */
#define GCC_PCIE_0_GDSC 0
#define GCC_UFS_PHY_GDSC 1
#define GCC_USB30_PRIM_GDSC 2
#define GCC_VCODEC0_GDSC 3
#define GCC_VENUS_GDSC 4
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_GPU_BCR 2
#define GCC_PCIE_0_BCR 3
#define GCC_PCIE_0_LINK_DOWN_BCR 4
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
#define GCC_PCIE_0_PHY_BCR 6
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
#define GCC_PCIE_PHY_BCR 8
#define GCC_PCIE_PHY_CFG_AHB_BCR 9
#define GCC_PCIE_PHY_COM_BCR 10
#define GCC_PDM_BCR 11
#define GCC_QUPV3_WRAPPER_0_BCR 12
#define GCC_QUPV3_WRAPPER_1_BCR 13
#define GCC_QUSB2PHY_PRIM_BCR 14
#define GCC_QUSB2PHY_SEC_BCR 15
#define GCC_SDCC1_BCR 16
#define GCC_SDCC2_BCR 17
#define GCC_UFS_PHY_BCR 18
#define GCC_USB30_PRIM_BCR 19
#define GCC_USB3_DP_PHY_PRIM_BCR 20
#define GCC_USB3_DP_PHY_SEC_BCR 21
#define GCC_USB3_PHY_PRIM_BCR 22
#define GCC_USB3_PHY_SEC_BCR 23
#define GCC_USB3PHY_PHY_PRIM_BCR 24
#define GCC_USB3PHY_PHY_SEC_BCR 25
#define GCC_VCODEC0_BCR 26
#define GCC_VENUS_BCR 27
#define GCC_VIDEO_BCR 28
#define GCC_VIDEO_VENUS_BCR 29
#define GCC_VENUS_CTL_AXI_CLK_ARES 30
#define GCC_VIDEO_VENUS_CTL_CLK_ARES 31
#endif

187
include/dt-bindings/clock/qcom,sm8550-camcc.h Normal file
View file

@ -0,0 +1,187 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_CLK 1
#define CAM_CC_BPS_CLK_SRC 2
#define CAM_CC_BPS_FAST_AHB_CLK 3
#define CAM_CC_CAMNOC_AXI_CLK 4
#define CAM_CC_CAMNOC_AXI_CLK_SRC 5
#define CAM_CC_CAMNOC_DCD_XO_CLK 6
#define CAM_CC_CAMNOC_XO_CLK 7
#define CAM_CC_CCI_0_CLK 8
#define CAM_CC_CCI_0_CLK_SRC 9
#define CAM_CC_CCI_1_CLK 10
#define CAM_CC_CCI_1_CLK_SRC 11
#define CAM_CC_CCI_2_CLK 12
#define CAM_CC_CCI_2_CLK_SRC 13
#define CAM_CC_CORE_AHB_CLK 14
#define CAM_CC_CPAS_AHB_CLK 15
#define CAM_CC_CPAS_BPS_CLK 16
#define CAM_CC_CPAS_CRE_CLK 17
#define CAM_CC_CPAS_FAST_AHB_CLK 18
#define CAM_CC_CPAS_IFE_0_CLK 19
#define CAM_CC_CPAS_IFE_1_CLK 20
#define CAM_CC_CPAS_IFE_2_CLK 21
#define CAM_CC_CPAS_IFE_LITE_CLK 22
#define CAM_CC_CPAS_IPE_NPS_CLK 23
#define CAM_CC_CPAS_SBI_CLK 24
#define CAM_CC_CPAS_SFE_0_CLK 25
#define CAM_CC_CPAS_SFE_1_CLK 26
#define CAM_CC_CPHY_RX_CLK_SRC 27
#define CAM_CC_CRE_AHB_CLK 28
#define CAM_CC_CRE_CLK 29
#define CAM_CC_CRE_CLK_SRC 30
#define CAM_CC_CSI0PHYTIMER_CLK 31
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 32
#define CAM_CC_CSI1PHYTIMER_CLK 33
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 34
#define CAM_CC_CSI2PHYTIMER_CLK 35
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 36
#define CAM_CC_CSI3PHYTIMER_CLK 37
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 38
#define CAM_CC_CSI4PHYTIMER_CLK 39
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 40
#define CAM_CC_CSI5PHYTIMER_CLK 41
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 42
#define CAM_CC_CSI6PHYTIMER_CLK 43
#define CAM_CC_CSI6PHYTIMER_CLK_SRC 44
#define CAM_CC_CSI7PHYTIMER_CLK 45
#define CAM_CC_CSI7PHYTIMER_CLK_SRC 46
#define CAM_CC_CSID_CLK 47
#define CAM_CC_CSID_CLK_SRC 48
#define CAM_CC_CSID_CSIPHY_RX_CLK 49
#define CAM_CC_CSIPHY0_CLK 50
#define CAM_CC_CSIPHY1_CLK 51
#define CAM_CC_CSIPHY2_CLK 52
#define CAM_CC_CSIPHY3_CLK 53
#define CAM_CC_CSIPHY4_CLK 54
#define CAM_CC_CSIPHY5_CLK 55
#define CAM_CC_CSIPHY6_CLK 56
#define CAM_CC_CSIPHY7_CLK 57
#define CAM_CC_DRV_AHB_CLK 58
#define CAM_CC_DRV_XO_CLK 59
#define CAM_CC_FAST_AHB_CLK_SRC 60
#define CAM_CC_GDSC_CLK 61
#define CAM_CC_ICP_AHB_CLK 62
#define CAM_CC_ICP_CLK 63
#define CAM_CC_ICP_CLK_SRC 64
#define CAM_CC_IFE_0_CLK 65
#define CAM_CC_IFE_0_CLK_SRC 66
#define CAM_CC_IFE_0_DSP_CLK 67
#define CAM_CC_IFE_0_DSP_CLK_SRC 68
#define CAM_CC_IFE_0_FAST_AHB_CLK 69
#define CAM_CC_IFE_1_CLK 70
#define CAM_CC_IFE_1_CLK_SRC 71
#define CAM_CC_IFE_1_DSP_CLK 72
#define CAM_CC_IFE_1_DSP_CLK_SRC 73
#define CAM_CC_IFE_1_FAST_AHB_CLK 74
#define CAM_CC_IFE_2_CLK 75
#define CAM_CC_IFE_2_CLK_SRC 76
#define CAM_CC_IFE_2_DSP_CLK 77
#define CAM_CC_IFE_2_DSP_CLK_SRC 78
#define CAM_CC_IFE_2_FAST_AHB_CLK 79
#define CAM_CC_IFE_LITE_AHB_CLK 80
#define CAM_CC_IFE_LITE_CLK 81
#define CAM_CC_IFE_LITE_CLK_SRC 82
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
#define CAM_CC_IFE_LITE_CSID_CLK 84
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
#define CAM_CC_IPE_NPS_AHB_CLK 86
#define CAM_CC_IPE_NPS_CLK 87
#define CAM_CC_IPE_NPS_CLK_SRC 88
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
#define CAM_CC_IPE_PPS_CLK 90
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
#define CAM_CC_JPEG_1_CLK 92
#define CAM_CC_JPEG_CLK 93
#define CAM_CC_JPEG_CLK_SRC 94
#define CAM_CC_MCLK0_CLK 95
#define CAM_CC_MCLK0_CLK_SRC 96
#define CAM_CC_MCLK1_CLK 97
#define CAM_CC_MCLK1_CLK_SRC 98
#define CAM_CC_MCLK2_CLK 99
#define CAM_CC_MCLK2_CLK_SRC 100
#define CAM_CC_MCLK3_CLK 101
#define CAM_CC_MCLK3_CLK_SRC 102
#define CAM_CC_MCLK4_CLK 103
#define CAM_CC_MCLK4_CLK_SRC 104
#define CAM_CC_MCLK5_CLK 105
#define CAM_CC_MCLK5_CLK_SRC 106
#define CAM_CC_MCLK6_CLK 107
#define CAM_CC_MCLK6_CLK_SRC 108
#define CAM_CC_MCLK7_CLK 109
#define CAM_CC_MCLK7_CLK_SRC 110
#define CAM_CC_PLL0 111
#define CAM_CC_PLL0_OUT_EVEN 112
#define CAM_CC_PLL0_OUT_ODD 113
#define CAM_CC_PLL1 114
#define CAM_CC_PLL1_OUT_EVEN 115
#define CAM_CC_PLL2 116
#define CAM_CC_PLL3 117
#define CAM_CC_PLL3_OUT_EVEN 118
#define CAM_CC_PLL4 119
#define CAM_CC_PLL4_OUT_EVEN 120
#define CAM_CC_PLL5 121
#define CAM_CC_PLL5_OUT_EVEN 122
#define CAM_CC_PLL6 123
#define CAM_CC_PLL6_OUT_EVEN 124
#define CAM_CC_PLL7 125
#define CAM_CC_PLL7_OUT_EVEN 126
#define CAM_CC_PLL8 127
#define CAM_CC_PLL8_OUT_EVEN 128
#define CAM_CC_PLL9 129
#define CAM_CC_PLL9_OUT_EVEN 130
#define CAM_CC_PLL10 131
#define CAM_CC_PLL10_OUT_EVEN 132
#define CAM_CC_PLL11 133
#define CAM_CC_PLL11_OUT_EVEN 134
#define CAM_CC_PLL12 135
#define CAM_CC_PLL12_OUT_EVEN 136
#define CAM_CC_QDSS_DEBUG_CLK 137
#define CAM_CC_QDSS_DEBUG_CLK_SRC 138
#define CAM_CC_QDSS_DEBUG_XO_CLK 139
#define CAM_CC_SBI_CLK 140
#define CAM_CC_SBI_FAST_AHB_CLK 141
#define CAM_CC_SFE_0_CLK 142
#define CAM_CC_SFE_0_CLK_SRC 143
#define CAM_CC_SFE_0_FAST_AHB_CLK 144
#define CAM_CC_SFE_1_CLK 145
#define CAM_CC_SFE_1_CLK_SRC 146
#define CAM_CC_SFE_1_FAST_AHB_CLK 147
#define CAM_CC_SLEEP_CLK 148
#define CAM_CC_SLEEP_CLK_SRC 149
#define CAM_CC_SLOW_AHB_CLK_SRC 150
#define CAM_CC_XO_CLK_SRC 151
/* CAM_CC power domains */
#define CAM_CC_BPS_GDSC 0
#define CAM_CC_IFE_0_GDSC 1
#define CAM_CC_IFE_1_GDSC 2
#define CAM_CC_IFE_2_GDSC 3
#define CAM_CC_IPE_0_GDSC 4
#define CAM_CC_SBI_GDSC 5
#define CAM_CC_SFE_0_GDSC 6
#define CAM_CC_SFE_1_GDSC 7
#define CAM_CC_TITAN_TOP_GDSC 8
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_DRV_BCR 1
#define CAM_CC_ICP_BCR 2
#define CAM_CC_IFE_0_BCR 3
#define CAM_CC_IFE_1_BCR 4
#define CAM_CC_IFE_2_BCR 5
#define CAM_CC_IPE_0_BCR 6
#define CAM_CC_QDSS_DEBUG_BCR 7
#define CAM_CC_SBI_BCR 8
#define CAM_CC_SFE_0_BCR 9
#define CAM_CC_SFE_1_BCR 10
#endif