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dmaengine late fixes for 5.3
Some late fixes for drivers: - memory leak in ti crossbar dma driver - cleanup of omap dma probe - Fix for link list configuration in sprd dma driver - Handling fixed for DMACHCLR if iommu is mapped in rcar dma -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdc2UTAAoJEHwUBw8lI4NHOyMP/R/rB6DdQ1TLbe+NciH/0WZT OL0oTSQ3K3pCiA9XqPa1VXaOwPo0w3151Fzd44pfhoQkKGXUpBNHDRSfsV4kvajA E9weDEfvatrsh9N5R7ml+sWpsu+dd28NyCIOydDVOx+QjS4f9qZyNcUsnKNKlEij N2ZCQpBozQa8kXhDymI5V1ldJSA8OzOqTgdRGKJFwg69hzpUSrkfSbjjhCubA943 LFLrQ1yp2lRwvd1HAKQutWGzzbXV9PiFCYWTcxHClaYjjhqNY/HBRppAw/Nfi4Qt C4JV2fi7IXTqNU5VJD6bfDtL4K2+oA0xkhuqdolrWFu0n1KBDDzC99zPEcjysQrK TWaGSNzR0oH9Xgk2IM75Srjorn3ErU5VSW0M8TSVBCoEj8Jt/R2GVFOrtCNMF8KN 7Lv48FZQsv8SoMeEgH6Kq4GuqRtFbqVzJdkeHpjfNe0hih5PNNW1+VM2RTkoJkPd qG7YavUqKbOTbR+QXVY9TLyV14/fp5OnDhrBWZ4vJxU0waHkxNbNLIlEChs8Pa9O 6UVnpl3bnKzDdFUEf6am5kjOEzTfxlbWcm5AA8rNyGHStDucgq/3c/FLZCuEPLtf VPrbR8oMe9iHZjRLwjSgVc1EjfWhmYeAOEBnAhi4duhgq+sXBfomrp8Y1B4voCkA m1UxFdLiAl+n1p4MQ9vA =rSgu -----END PGP SIGNATURE----- Merge tag 'dmaengine-fix-5.3' of git://git.infradead.org/users/vkoul/slave-dma Pull dmaengine fixes from Vinod Koul: "Some late fixes for drivers: - memory leak in ti crossbar dma driver - cleanup of omap dma probe - Fix for link list configuration in sprd dma driver - Handling fixed for DMACHCLR if iommu is mapped in rcar dma" * tag 'dmaengine-fix-5.3' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: rcar-dmac: Fix DMACHCLR handling if iommu is mapped dmaengine: sprd: Fix the DMA link-list configuration dmaengine: ti: omap-dma: Add cleanup in omap_dma_probe() dmaengine: ti: dma-crossbar: Fix a memory leak bug
This commit is contained in:
Linus Torvalds
commit
d3464ccd10
4 changed files with 33 additions and 13 deletions
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@ -192,6 +192,7 @@ struct rcar_dmac_chan {
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* @iomem: remapped I/O memory base
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* @n_channels: number of available channels
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* @channels: array of DMAC channels
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* @channels_mask: bitfield of which DMA channels are managed by this driver
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* @modules: bitmask of client modules in use
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*/
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struct rcar_dmac {
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@ -202,6 +203,7 @@ struct rcar_dmac {
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unsigned int n_channels;
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struct rcar_dmac_chan *channels;
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unsigned int channels_mask;
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DECLARE_BITMAP(modules, 256);
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};
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@ -438,7 +440,7 @@ static int rcar_dmac_init(struct rcar_dmac *dmac)
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u16 dmaor;
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/* Clear all channels and enable the DMAC globally. */
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rcar_dmac_write(dmac, RCAR_DMACHCLR, GENMASK(dmac->n_channels - 1, 0));
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rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
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rcar_dmac_write(dmac, RCAR_DMAOR,
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RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
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@ -814,6 +816,9 @@ static void rcar_dmac_stop_all_chan(struct rcar_dmac *dmac)
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for (i = 0; i < dmac->n_channels; ++i) {
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struct rcar_dmac_chan *chan = &dmac->channels[i];
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if (!(dmac->channels_mask & BIT(i)))
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continue;
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/* Stop and reinitialize the channel. */
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spin_lock_irq(&chan->lock);
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rcar_dmac_chan_halt(chan);
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@ -1776,6 +1781,8 @@ static int rcar_dmac_chan_probe(struct rcar_dmac *dmac,
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return 0;
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}
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#define RCAR_DMAC_MAX_CHANNELS 32
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static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
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{
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struct device_node *np = dev->of_node;
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@ -1787,12 +1794,16 @@ static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
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return ret;
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}
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if (dmac->n_channels <= 0 || dmac->n_channels >= 100) {
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/* The hardware and driver don't support more than 32 bits in CHCLR */
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if (dmac->n_channels <= 0 ||
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dmac->n_channels >= RCAR_DMAC_MAX_CHANNELS) {
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dev_err(dev, "invalid number of channels %u\n",
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dmac->n_channels);
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return -EINVAL;
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}
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dmac->channels_mask = GENMASK(dmac->n_channels - 1, 0);
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return 0;
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}
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@ -1802,7 +1813,6 @@ static int rcar_dmac_probe(struct platform_device *pdev)
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DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES |
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DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES |
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DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES;
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unsigned int channels_offset = 0;
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struct dma_device *engine;
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struct rcar_dmac *dmac;
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struct resource *mem;
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@ -1831,10 +1841,8 @@ static int rcar_dmac_probe(struct platform_device *pdev)
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* level we can't disable it selectively, so ignore channel 0 for now if
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* the device is part of an IOMMU group.
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*/
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if (device_iommu_mapped(&pdev->dev)) {
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dmac->n_channels--;
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channels_offset = 1;
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}
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if (device_iommu_mapped(&pdev->dev))
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dmac->channels_mask &= ~BIT(0);
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dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
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sizeof(*dmac->channels), GFP_KERNEL);
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@ -1892,8 +1900,10 @@ static int rcar_dmac_probe(struct platform_device *pdev)
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INIT_LIST_HEAD(&engine->channels);
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for (i = 0; i < dmac->n_channels; ++i) {
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ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i],
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i + channels_offset);
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if (!(dmac->channels_mask & BIT(i)))
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continue;
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ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i], i);
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if (ret < 0)
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goto error;
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}
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@ -908,6 +908,7 @@ sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
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struct dma_slave_config *slave_cfg = &schan->slave_cfg;
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dma_addr_t src = 0, dst = 0;
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dma_addr_t start_src = 0, start_dst = 0;
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struct sprd_dma_desc *sdesc;
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struct scatterlist *sg;
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u32 len = 0;
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@ -954,6 +955,11 @@ sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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dst = sg_dma_address(sg);
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}
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if (!i) {
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start_src = src;
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start_dst = dst;
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}
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/*
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* The link-list mode needs at least 2 link-list
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* configurations. If there is only one sg, it doesn't
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@ -970,8 +976,8 @@ sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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}
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}
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ret = sprd_dma_fill_desc(chan, &sdesc->chn_hw, 0, 0, src, dst, len,
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dir, flags, slave_cfg);
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ret = sprd_dma_fill_desc(chan, &sdesc->chn_hw, 0, 0, start_src,
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start_dst, len, dir, flags, slave_cfg);
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if (ret) {
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kfree(sdesc);
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return NULL;
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@ -391,8 +391,10 @@ static int ti_dra7_xbar_probe(struct platform_device *pdev)
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ret = of_property_read_u32_array(node, pname, (u32 *)rsv_events,
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nelm * 2);
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if (ret)
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if (ret) {
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kfree(rsv_events);
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return ret;
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}
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for (i = 0; i < nelm; i++) {
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ti_dra7_xbar_reserve(rsv_events[i][0], rsv_events[i][1],
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@ -1540,8 +1540,10 @@ static int omap_dma_probe(struct platform_device *pdev)
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rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq,
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IRQF_SHARED, "omap-dma-engine", od);
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if (rc)
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if (rc) {
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omap_dma_free(od);
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return rc;
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}
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}
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if (omap_dma_glbl_read(od, CAPS_0) & CAPS_0_SUPPORT_LL123)
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