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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ALSA: ctxfi - Fix / clean up hw20k2 chip code
- Clean up Hungarian coding style - Don't use static variables for I2C information; this unables to use multiple instances. Now they are stored in struct hw20k2 fields. Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Takashi Iwai
parent
af8500bbbd
commit
d362af62ed
1 changed files with 177 additions and 169 deletions
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@ -15,8 +15,6 @@
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*
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*/
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#include "cthw20k2.h"
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#include "ct20k2reg.h"
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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@ -25,6 +23,8 @@
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include "cthw20k2.h"
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#include "ct20k2reg.h"
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#if BITS_PER_LONG == 32
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#define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */
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@ -32,6 +32,14 @@
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#define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */
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#endif
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struct hw20k2 {
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struct hw hw;
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/* for i2c */
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unsigned char dev_id;
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unsigned char addr_size;
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unsigned char data_size;
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};
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static u32 hw_read_20kx(struct hw *hw, u32 reg);
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static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
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@ -1125,7 +1133,7 @@ struct trn_conf {
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static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
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{
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u32 dwData;
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u32 data;
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int i;
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/* Program I2S with proper sample rate and enable the correct I2S
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@ -1156,12 +1164,12 @@ static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
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if (i <= 3) {
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/* 1st 3 channels are SPDIFs (SB0960) */
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if (i == 3)
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dwData = 0x1001001;
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data = 0x1001001;
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else
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dwData = 0x1000001;
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data = 0x1000001;
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hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), dwData);
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hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), dwData);
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hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
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hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
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/* Initialize the SPDIF Out Channel status registers.
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* The value specified here is based on the typical
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@ -1179,13 +1187,13 @@ static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
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hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
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} else {
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/* Next 5 channels are I2S (SB0960) */
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dwData = 0x11;
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hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), dwData);
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data = 0x11;
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hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
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if (2 == info->msr) {
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/* Four channels per sample period */
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dwData |= 0x1000;
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data |= 0x1000;
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}
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hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), dwData);
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hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
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}
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}
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@ -1377,34 +1385,32 @@ static int hw_auto_init(struct hw *hw)
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#define I2C_ADDRESS_PTAD 0x0000FFFF
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#define I2C_ADDRESS_SLAD 0x007F0000
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struct REGS_CS4382 {
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u32 dwModeControl_1;
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u32 dwModeControl_2;
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u32 dwModeControl_3;
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struct regs_cs4382 {
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u32 mode_control_1;
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u32 mode_control_2;
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u32 mode_control_3;
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u32 dwFilterControl;
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u32 dwInvertControl;
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u32 filter_control;
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u32 invert_control;
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u32 dwMixControl_P1;
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u32 dwVolControl_A1;
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u32 dwVolControl_B1;
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u32 mix_control_P1;
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u32 vol_control_A1;
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u32 vol_control_B1;
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u32 dwMixControl_P2;
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u32 dwVolControl_A2;
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u32 dwVolControl_B2;
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u32 mix_control_P2;
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u32 vol_control_A2;
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u32 vol_control_B2;
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u32 dwMixControl_P3;
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u32 dwVolControl_A3;
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u32 dwVolControl_B3;
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u32 mix_control_P3;
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u32 vol_control_A3;
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u32 vol_control_B3;
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u32 dwMixControl_P4;
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u32 dwVolControl_A4;
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u32 dwVolControl_B4;
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u32 mix_control_P4;
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u32 vol_control_A4;
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u32 vol_control_B4;
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};
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static u8 m_bAddressSize, m_bDataSize, m_bDeviceID;
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static int I2CUnlockFullAccess(struct hw *hw)
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static int hw20k2_i2c_unlock_full_access(struct hw *hw)
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{
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u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
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@ -1420,7 +1426,7 @@ static int I2CUnlockFullAccess(struct hw *hw)
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return -1;
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}
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static int I2CLockChip(struct hw *hw)
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static int hw20k2_i2c_lock_chip(struct hw *hw)
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{
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/* Write twice */
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hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
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@ -1431,54 +1437,55 @@ static int I2CLockChip(struct hw *hw)
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return -1;
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}
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static int I2CInit(struct hw *hw, u8 bDeviceID, u8 bAddressSize, u8 bDataSize)
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static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
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{
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struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
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int err;
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unsigned int RegI2CStatus;
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unsigned int RegI2CAddress;
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unsigned int i2c_status;
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unsigned int i2c_addr;
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err = I2CUnlockFullAccess(hw);
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err = hw20k2_i2c_unlock_full_access(hw);
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if (err < 0)
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return err;
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m_bAddressSize = bAddressSize;
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m_bDataSize = bDataSize;
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m_bDeviceID = bDeviceID;
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hw20k2->addr_size = addr_size;
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hw20k2->data_size = data_size;
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hw20k2->dev_id = dev_id;
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RegI2CAddress = 0;
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set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, bDeviceID);
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i2c_addr = 0;
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set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
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hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
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hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
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RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
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i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
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set_field(&RegI2CStatus, I2C_STATUS_DCM, 1); /* Direct control mode */
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set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */
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hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
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hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
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return 0;
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}
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static int I2CUninit(struct hw *hw)
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static int hw20k2_i2c_uninit(struct hw *hw)
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{
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unsigned int RegI2CStatus;
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unsigned int RegI2CAddress;
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unsigned int i2c_status;
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unsigned int i2c_addr;
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RegI2CAddress = 0;
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set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
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i2c_addr = 0;
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set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
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hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
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hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
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RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
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i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
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set_field(&RegI2CStatus, I2C_STATUS_DCM, 0); /* I2C mode */
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set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */
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hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
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hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
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return I2CLockChip(hw);
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return hw20k2_i2c_lock_chip(hw);
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}
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static int I2CWaitDataReady(struct hw *hw)
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static int hw20k2_i2c_wait_data_ready(struct hw *hw)
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{
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int i = 0x400000;
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unsigned int ret;
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@ -1490,51 +1497,53 @@ static int I2CWaitDataReady(struct hw *hw)
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return i;
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}
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static int I2CRead(struct hw *hw, u16 wAddress, u32 *pdwData)
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static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
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{
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unsigned int RegI2CStatus;
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struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
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unsigned int i2c_status;
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RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
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set_field(&RegI2CStatus, I2C_STATUS_BC,
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(4 == m_bAddressSize) ? 0 : m_bAddressSize);
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hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
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if (!I2CWaitDataReady(hw))
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i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
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set_field(&i2c_status, I2C_STATUS_BC,
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(4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
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hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
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if (!hw20k2_i2c_wait_data_ready(hw))
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return -1;
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hw_write_20kx(hw, I2C_IF_WDATA, (u32)wAddress);
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if (!I2CWaitDataReady(hw))
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hw_write_20kx(hw, I2C_IF_WDATA, addr);
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if (!hw20k2_i2c_wait_data_ready(hw))
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return -1;
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/* Force a read operation */
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hw_write_20kx(hw, I2C_IF_RDATA, 0);
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if (!I2CWaitDataReady(hw))
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if (!hw20k2_i2c_wait_data_ready(hw))
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return -1;
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*pdwData = hw_read_20kx(hw, I2C_IF_RDATA);
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*datap = hw_read_20kx(hw, I2C_IF_RDATA);
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return 0;
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}
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static int I2CWrite(struct hw *hw, u16 wAddress, u32 dwData)
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static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
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{
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unsigned int dwI2CData = (dwData << (m_bAddressSize * 8)) | wAddress;
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unsigned int RegI2CStatus;
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struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
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unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
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unsigned int i2c_status;
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RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
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i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
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set_field(&RegI2CStatus, I2C_STATUS_BC,
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(4 == (m_bAddressSize + m_bDataSize)) ?
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0 : (m_bAddressSize + m_bDataSize));
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set_field(&i2c_status, I2C_STATUS_BC,
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(4 == (hw20k2->addr_size + hw20k2->data_size)) ?
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0 : (hw20k2->addr_size + hw20k2->data_size));
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hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
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I2CWaitDataReady(hw);
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hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
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hw20k2_i2c_wait_data_ready(hw);
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/* Dummy write to trigger the write oprtation */
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hw_write_20kx(hw, I2C_IF_WDATA, 0);
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I2CWaitDataReady(hw);
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hw20k2_i2c_wait_data_ready(hw);
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/* This is the real data */
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hw_write_20kx(hw, I2C_IF_WDATA, dwI2CData);
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I2CWaitDataReady(hw);
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hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
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hw20k2_i2c_wait_data_ready(hw);
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return 0;
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}
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@ -1542,10 +1551,10 @@ static int I2CWrite(struct hw *hw, u16 wAddress, u32 dwData)
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static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
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{
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int err;
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u32 dwData;
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u32 data;
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int i;
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struct REGS_CS4382 cs4382_Read = {0};
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struct REGS_CS4382 cs4382_Def = {
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struct regs_cs4382 cs_read = {0};
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struct regs_cs4382 cs_def = {
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0x00000001, /* Mode Control 1 */
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0x00000000, /* Mode Control 2 */
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0x00000084, /* Mode Control 3 */
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@ -1566,87 +1575,86 @@ static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
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};
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/* Set DAC reset bit as output */
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dwData = hw_read_20kx(hw, GPIO_CTRL);
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dwData |= 0x02;
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hw_write_20kx(hw, GPIO_CTRL, dwData);
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data = hw_read_20kx(hw, GPIO_CTRL);
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data |= 0x02;
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hw_write_20kx(hw, GPIO_CTRL, data);
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err = I2CInit(hw, 0x18, 1, 1);
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err = hw20k2_i2c_init(hw, 0x18, 1, 1);
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if (err < 0)
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goto End;
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for (i = 0; i < 2; i++) {
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/* Reset DAC twice just in-case the chip
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* didn't initialized properly */
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dwData = hw_read_20kx(hw, GPIO_DATA);
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data = hw_read_20kx(hw, GPIO_DATA);
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/* GPIO data bit 1 */
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dwData &= 0xFFFFFFFD;
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hw_write_20kx(hw, GPIO_DATA, dwData);
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data &= 0xFFFFFFFD;
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hw_write_20kx(hw, GPIO_DATA, data);
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mdelay(10);
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dwData |= 0x2;
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hw_write_20kx(hw, GPIO_DATA, dwData);
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data |= 0x2;
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hw_write_20kx(hw, GPIO_DATA, data);
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mdelay(50);
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/* Reset the 2nd time */
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dwData &= 0xFFFFFFFD;
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hw_write_20kx(hw, GPIO_DATA, dwData);
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data &= 0xFFFFFFFD;
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hw_write_20kx(hw, GPIO_DATA, data);
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mdelay(10);
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dwData |= 0x2;
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hw_write_20kx(hw, GPIO_DATA, dwData);
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data |= 0x2;
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hw_write_20kx(hw, GPIO_DATA, data);
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mdelay(50);
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if (I2CRead(hw, CS4382_MC1, &cs4382_Read.dwModeControl_1))
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if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1))
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continue;
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if (I2CRead(hw, CS4382_MC2, &cs4382_Read.dwModeControl_2))
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if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2))
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continue;
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if (I2CRead(hw, CS4382_MC3, &cs4382_Read.dwModeControl_3))
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if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3))
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continue;
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if (I2CRead(hw, CS4382_FC, &cs4382_Read.dwFilterControl))
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if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control))
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continue;
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if (I2CRead(hw, CS4382_IC, &cs4382_Read.dwInvertControl))
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if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control))
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continue;
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if (I2CRead(hw, CS4382_XC1, &cs4382_Read.dwMixControl_P1))
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if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1))
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continue;
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if (I2CRead(hw, CS4382_VCA1, &cs4382_Read.dwVolControl_A1))
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if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
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continue;
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if (I2CRead(hw, CS4382_VCB1, &cs4382_Read.dwVolControl_B1))
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if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
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continue;
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if (I2CRead(hw, CS4382_XC2, &cs4382_Read.dwMixControl_P2))
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if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2))
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continue;
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|
||||
if (I2CRead(hw, CS4382_VCA2, &cs4382_Read.dwVolControl_A2))
|
||||
if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
|
||||
continue;
|
||||
|
||||
if (I2CRead(hw, CS4382_VCB2, &cs4382_Read.dwVolControl_B2))
|
||||
if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
|
||||
continue;
|
||||
|
||||
if (I2CRead(hw, CS4382_XC3, &cs4382_Read.dwMixControl_P3))
|
||||
if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3))
|
||||
continue;
|
||||
|
||||
if (I2CRead(hw, CS4382_VCA3, &cs4382_Read.dwVolControl_A3))
|
||||
if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
|
||||
continue;
|
||||
|
||||
if (I2CRead(hw, CS4382_VCB3, &cs4382_Read.dwVolControl_B3))
|
||||
if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
|
||||
continue;
|
||||
|
||||
if (I2CRead(hw, CS4382_XC4, &cs4382_Read.dwMixControl_P4))
|
||||
if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4))
|
||||
continue;
|
||||
|
||||
if (I2CRead(hw, CS4382_VCA4, &cs4382_Read.dwVolControl_A4))
|
||||
if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
|
||||
continue;
|
||||
|
||||
if (I2CRead(hw, CS4382_VCB4, &cs4382_Read.dwVolControl_B4))
|
||||
if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
|
||||
continue;
|
||||
|
||||
if (memcmp(&cs4382_Read, &cs4382_Def,
|
||||
sizeof(struct REGS_CS4382)))
|
||||
if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
|
||||
continue;
|
||||
else
|
||||
break;
|
||||
|
|
@ -1657,29 +1665,29 @@ static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
|
|||
|
||||
/* Note: Every I2C write must have some delay.
|
||||
* This is not a requirement but the delay works here... */
|
||||
I2CWrite(hw, CS4382_MC1, 0x80);
|
||||
I2CWrite(hw, CS4382_MC2, 0x10);
|
||||
hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
|
||||
hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
|
||||
if (1 == info->msr) {
|
||||
I2CWrite(hw, CS4382_XC1, 0x24);
|
||||
I2CWrite(hw, CS4382_XC2, 0x24);
|
||||
I2CWrite(hw, CS4382_XC3, 0x24);
|
||||
I2CWrite(hw, CS4382_XC4, 0x24);
|
||||
hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
|
||||
hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
|
||||
hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
|
||||
hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
|
||||
} else if (2 == info->msr) {
|
||||
I2CWrite(hw, CS4382_XC1, 0x25);
|
||||
I2CWrite(hw, CS4382_XC2, 0x25);
|
||||
I2CWrite(hw, CS4382_XC3, 0x25);
|
||||
I2CWrite(hw, CS4382_XC4, 0x25);
|
||||
hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
|
||||
hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
|
||||
hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
|
||||
hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
|
||||
} else {
|
||||
I2CWrite(hw, CS4382_XC1, 0x26);
|
||||
I2CWrite(hw, CS4382_XC2, 0x26);
|
||||
I2CWrite(hw, CS4382_XC3, 0x26);
|
||||
I2CWrite(hw, CS4382_XC4, 0x26);
|
||||
hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
|
||||
hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
|
||||
hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
|
||||
hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
|
||||
}
|
||||
|
||||
return 0;
|
||||
End:
|
||||
|
||||
I2CUninit(hw);
|
||||
hw20k2_i2c_uninit(hw);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
@ -1721,21 +1729,21 @@ static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
|
|||
case ADC_MICIN:
|
||||
data |= (0x1 << 14);
|
||||
hw_write_20kx(hw, GPIO_DATA, data);
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
|
||||
MAKE_WM8775_DATA(0x101)); /* Mic-in */
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
|
||||
MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
|
||||
MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
|
||||
break;
|
||||
case ADC_LINEIN:
|
||||
data &= ~(0x1 << 14);
|
||||
hw_write_20kx(hw, GPIO_DATA, data);
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
|
||||
MAKE_WM8775_DATA(0x102)); /* Line-in */
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
|
||||
MAKE_WM8775_DATA(0xCF)); /* No boost */
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
|
||||
MAKE_WM8775_DATA(0xCF)); /* No boost */
|
||||
break;
|
||||
default:
|
||||
|
|
@ -1748,34 +1756,34 @@ static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
|
|||
static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
|
||||
{
|
||||
int err;
|
||||
u32 dwMux = 2, dwData, dwCtl;
|
||||
u32 mux = 2, data, ctl;
|
||||
|
||||
/* Set ADC reset bit as output */
|
||||
dwData = hw_read_20kx(hw, GPIO_CTRL);
|
||||
dwData |= (0x1 << 15);
|
||||
hw_write_20kx(hw, GPIO_CTRL, dwData);
|
||||
data = hw_read_20kx(hw, GPIO_CTRL);
|
||||
data |= (0x1 << 15);
|
||||
hw_write_20kx(hw, GPIO_CTRL, data);
|
||||
|
||||
/* Initialize I2C */
|
||||
err = I2CInit(hw, 0x1A, 1, 1);
|
||||
err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
|
||||
if (err < 0) {
|
||||
printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
/* Make ADC in normal operation */
|
||||
dwData = hw_read_20kx(hw, GPIO_DATA);
|
||||
dwData &= ~(0x1 << 15);
|
||||
data = hw_read_20kx(hw, GPIO_DATA);
|
||||
data &= ~(0x1 << 15);
|
||||
mdelay(10);
|
||||
dwData |= (0x1 << 15);
|
||||
hw_write_20kx(hw, GPIO_DATA, dwData);
|
||||
data |= (0x1 << 15);
|
||||
hw_write_20kx(hw, GPIO_DATA, data);
|
||||
mdelay(50);
|
||||
|
||||
/* Set the master mode (256fs) */
|
||||
if (1 == info->msr) {
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
|
||||
MAKE_WM8775_DATA(0x02));
|
||||
} else if (2 == info->msr) {
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
|
||||
MAKE_WM8775_DATA(0x0A));
|
||||
} else {
|
||||
printk(KERN_ALERT "ctxfi: Invalid master sampling "
|
||||
|
|
@ -1785,35 +1793,35 @@ static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
|
|||
}
|
||||
|
||||
/* Configure GPIO bit 14 change to line-in/mic-in */
|
||||
dwCtl = hw_read_20kx(hw, GPIO_CTRL);
|
||||
dwCtl |= 0x1<<14;
|
||||
hw_write_20kx(hw, GPIO_CTRL, dwCtl);
|
||||
ctl = hw_read_20kx(hw, GPIO_CTRL);
|
||||
ctl |= 0x1 << 14;
|
||||
hw_write_20kx(hw, GPIO_CTRL, ctl);
|
||||
|
||||
/* Check using Mic-in or Line-in */
|
||||
dwData = hw_read_20kx(hw, GPIO_DATA);
|
||||
data = hw_read_20kx(hw, GPIO_DATA);
|
||||
|
||||
if (dwMux == 1) {
|
||||
if (mux == 1) {
|
||||
/* Configures GPIO data to select Mic-in */
|
||||
dwData |= 0x1<<14;
|
||||
hw_write_20kx(hw, GPIO_DATA, dwData);
|
||||
data |= 0x1 << 14;
|
||||
hw_write_20kx(hw, GPIO_DATA, data);
|
||||
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
|
||||
MAKE_WM8775_DATA(0x101)); /* Mic-in */
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
|
||||
MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
|
||||
MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
|
||||
} else if (dwMux == 2) {
|
||||
} else if (mux == 2) {
|
||||
/* Configures GPIO data to select Line-in */
|
||||
dwData &= ~(0x1<<14);
|
||||
hw_write_20kx(hw, GPIO_DATA, dwData);
|
||||
data &= ~(0x1 << 14);
|
||||
hw_write_20kx(hw, GPIO_DATA, data);
|
||||
|
||||
/* Setup ADC */
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
|
||||
MAKE_WM8775_DATA(0x102)); /* Line-in */
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
|
||||
MAKE_WM8775_DATA(0xCF)); /* No boost */
|
||||
I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
|
||||
hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
|
||||
MAKE_WM8775_DATA(0xCF)); /* No boost */
|
||||
} else {
|
||||
printk(KERN_ALERT "ctxfi: ERROR!!! Invalid input mux!!!\n");
|
||||
|
|
@ -1824,7 +1832,7 @@ static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
|
|||
return 0;
|
||||
|
||||
error:
|
||||
I2CUninit(hw);
|
||||
hw20k2_i2c_uninit(hw);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
@ -2106,15 +2114,15 @@ static struct hw ct20k2_preset __devinitdata = {
|
|||
|
||||
int __devinit create_20k2_hw_obj(struct hw **rhw)
|
||||
{
|
||||
struct hw *hw;
|
||||
struct hw20k2 *hw20k2;
|
||||
|
||||
*rhw = NULL;
|
||||
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
|
||||
if (NULL == hw)
|
||||
hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL);
|
||||
if (!hw20k2)
|
||||
return -ENOMEM;
|
||||
|
||||
*hw = ct20k2_preset;
|
||||
*rhw = hw;
|
||||
hw20k2->hw = ct20k2_preset;
|
||||
*rhw = &hw20k2->hw;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue