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can: flexcan: flexcan_read_reg_iflag_rx(): optimize reading

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The flexcan IP core has up to 64 mailboxes, each one has a corresponding
interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
imask1 or imask2 registers.

In the timestamp (i.e. non FIFO) mode the driver needs to mask all non RX
interrupt sources, it uses the precomputed value rx_mask of struct flexcan_priv
for this.

In certain use cases, for example the CANFD mode, the contents of the iflag2
register is completely masked.

This patch optimizes the flexcan_read_reg_iflag_rx() function by not reading
the iflag1 or iflag2 register if the contents is masked.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Marc Kleine-Budde 2019-03-01 15:38:05 +01:00
parent 0ca64f02de
commit d3a51507e4
1 changed files with 17 additions and 11 deletions
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28
drivers/net/can/flexcan.c
View file

@ -778,6 +778,23 @@ static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
dev->stats.rx_fifo_errors++;
}
static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
{
u64 reg = 0;
if (upper_32_bits(mask))
reg = (u64)priv->read(addr - 4) << 32;
if (lower_32_bits(mask))
reg |= priv->read(addr);
return reg & mask;
}
static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
{
return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
}
static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
{
return container_of(offload, struct flexcan_priv, offload);
@ -872,17 +889,6 @@ static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
return skb;
}
static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
{
struct flexcan_regs __iomem *regs = priv->regs;
u64 iflag;
iflag = (u64)priv->read(&regs->iflag2) << 32 |
priv->read(&regs->iflag1);
return iflag & priv->rx_mask;
}
static irqreturn_t flexcan_irq(int irq, void *dev_id)
{
struct net_device *dev = dev_id;