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serial: max310x: Migrate to CLK API
This patch removes "frequency" parameter from MAX310X platform_data and uses CLK API for getting clock. Clock type (XTAL/OSC) is determined by clk name. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alexander Shiyan
Greg Kroah-Hartman
parent
27027a70e2
commit
d3a8a252e1
2 changed files with 55 additions and 38 deletions
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@ -17,6 +17,7 @@
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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@ -291,6 +292,7 @@ struct max310x_port {
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struct max310x_devtype *devtype;
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struct regmap *regmap;
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struct mutex mutex;
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struct clk *clk;
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struct max310x_pdata *pdata;
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int gpio_used;
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#ifdef CONFIG_GPIOLIB
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@ -546,18 +548,19 @@ static int max310x_update_best_err(unsigned long f, long *besterr)
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return 1;
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}
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static int max310x_set_ref_clk(struct max310x_port *s)
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static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq,
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bool xtal)
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{
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unsigned int div, clksrc, pllcfg = 0;
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long besterr = -1;
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unsigned long fdiv, fmul, bestfreq = s->pdata->frequency;
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unsigned long fdiv, fmul, bestfreq = freq;
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/* First, update error without PLL */
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max310x_update_best_err(s->pdata->frequency, &besterr);
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max310x_update_best_err(freq, &besterr);
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/* Try all possible PLL dividers */
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for (div = 1; (div <= 63) && besterr; div++) {
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fdiv = DIV_ROUND_CLOSEST(s->pdata->frequency, div);
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fdiv = DIV_ROUND_CLOSEST(freq, div);
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/* Try multiplier 6 */
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fmul = fdiv * 6;
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@ -590,10 +593,7 @@ static int max310x_set_ref_clk(struct max310x_port *s)
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}
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/* Configure clock source */
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if (s->pdata->driver_flags & MAX310X_EXT_CLK)
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clksrc = MAX310X_CLKSRC_EXTCLK_BIT;
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else
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clksrc = MAX310X_CLKSRC_CRYST_BIT;
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clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT;
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/* Configure PLL */
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if (pllcfg) {
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@ -605,7 +605,7 @@ static int max310x_set_ref_clk(struct max310x_port *s)
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regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
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/* Wait for crystal */
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if (pllcfg && !(s->pdata->driver_flags & MAX310X_EXT_CLK))
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if (pllcfg && xtal)
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msleep(10);
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return (int)bestfreq;
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@ -1078,9 +1078,11 @@ static int max310x_gpio_direction_output(struct gpio_chip *chip,
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static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
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struct regmap *regmap, int irq)
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{
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struct max310x_port *s;
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struct max310x_pdata *pdata = dev_get_platdata(dev);
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int i, ret, uartclk;
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int i, ret, fmin, fmax, freq, uartclk;
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struct clk *clk_osc, *clk_xtal;
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struct max310x_port *s;
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bool xtal = false;
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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@ -1098,14 +1100,35 @@ static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
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return -ENOMEM;
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}
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/* Check input frequency */
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if ((pdata->driver_flags & MAX310X_EXT_CLK) &&
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((pdata->frequency < 500000) || (pdata->frequency > 35000000)))
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goto err_freq;
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/* Check frequency for quartz */
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if (!(pdata->driver_flags & MAX310X_EXT_CLK) &&
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((pdata->frequency < 1000000) || (pdata->frequency > 4000000)))
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goto err_freq;
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clk_osc = devm_clk_get(dev, "osc");
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clk_xtal = devm_clk_get(dev, "xtal");
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if (!IS_ERR(clk_osc)) {
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s->clk = clk_osc;
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fmin = 500000;
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fmax = 35000000;
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} else if (!IS_ERR(clk_xtal)) {
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s->clk = clk_xtal;
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fmin = 1000000;
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fmax = 4000000;
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xtal = true;
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} else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
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PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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} else {
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dev_err(dev, "Cannot get clock\n");
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return -EINVAL;
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}
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ret = clk_prepare_enable(s->clk);
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if (ret)
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return ret;
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freq = clk_get_rate(s->clk);
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/* Check frequency limits */
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if (freq < fmin || freq > fmax) {
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ret = -ERANGE;
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goto out_clk;
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}
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s->pdata = pdata;
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s->regmap = regmap;
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@ -1117,7 +1140,7 @@ static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
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/* Check device to ensure we are talking to what we expect */
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ret = devtype->detect(dev);
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if (ret)
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return ret;
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goto out_clk;
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for (i = 0; i < devtype->nr; i++) {
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unsigned int offs = i << 5;
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@ -1139,7 +1162,7 @@ static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
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MAX310X_MODE1_AUTOSLEEP_BIT);
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}
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uartclk = max310x_set_ref_clk(s);
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uartclk = max310x_set_ref_clk(s, freq, xtal);
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dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
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/* Register UART driver */
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@ -1151,7 +1174,7 @@ static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
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ret = uart_register_driver(&s->uart);
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if (ret) {
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dev_err(dev, "Registering UART driver failed\n");
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return ret;
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goto out_clk;
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}
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for (i = 0; i < devtype->nr; i++) {
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@ -1208,19 +1231,19 @@ static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
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ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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dev_name(dev), s);
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if (ret) {
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dev_err(dev, "Unable to reguest IRQ %i\n", irq);
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if (!ret)
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return 0;
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dev_err(dev, "Unable to reguest IRQ %i\n", irq);
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#ifdef CONFIG_GPIOLIB
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if (s->gpio_used)
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WARN_ON(gpiochip_remove(&s->gpio));
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if (s->gpio_used)
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WARN_ON(gpiochip_remove(&s->gpio));
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#endif
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}
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out_clk:
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clk_disable_unprepare(s->clk);
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return ret;
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err_freq:
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dev_err(dev, "Frequency parameter incorrect\n");
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return -EINVAL;
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}
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static int max310x_remove(struct device *dev)
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@ -1236,6 +1259,7 @@ static int max310x_remove(struct device *dev)
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}
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uart_unregister_driver(&s->uart);
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clk_disable_unprepare(s->clk);
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#ifdef CONFIG_GPIOLIB
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if (s->gpio_used)
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@ -20,9 +20,7 @@
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* Example board initialization data:
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*
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* static struct max310x_pdata max3107_pdata = {
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* .driver_flags = MAX310X_EXT_CLK,
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* .uart_flags[0] = MAX310X_ECHO_SUPRESS | MAX310X_AUTO_DIR_CTRL,
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* .frequency = 3686400,
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* .gpio_base = -1,
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* };
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*
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@ -41,17 +39,12 @@
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/* MAX310X platform data structure */
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struct max310x_pdata {
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/* Flags global to driver */
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const u8 driver_flags;
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#define MAX310X_EXT_CLK (0x00000001) /* External clock enable */
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/* Flags global to UART port */
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const u8 uart_flags[MAX310X_MAX_UARTS];
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#define MAX310X_ECHO_SUPRESS (0x00000002) /* Enable echo supress */
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#define MAX310X_AUTO_DIR_CTRL (0x00000004) /* Enable Auto direction
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* control (RS-485)
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*/
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/* Frequency (extrenal clock or crystal) */
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const int frequency;
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/* GPIO base number (can be negative) */
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const int gpio_base;
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};
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