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irqchip/gic-v3-its: Flush ITS tables correctly in non-coherent GIC designs
In non-coherent GIC designs, the ITS tables must be flushed before writing
to the GITS_BASER<n> registers, otherwise the ITS could read dirty tables,
which results in unpredictable behavior.
Flush the tables right at the begin of its_setup_baser() to prevent that.
[ tglx: Massage changelog ]
Fixes: a8707f5538
("irqchip/gic-v3: Add Rockchip 3588001 erratum workaround")
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20231030083256.4345-1-fangxiang3@xiaomi.com
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parent
8999ad99f4
commit
d3badb1561
1 changed files with 10 additions and 6 deletions
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@ -2379,12 +2379,12 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
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break;
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}
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if (!shr)
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gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
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its_write_baser(its, baser, val);
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tmp = baser->val;
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if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
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tmp &= ~GITS_BASER_SHAREABILITY_MASK;
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if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
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/*
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* Shareability didn't stick. Just use
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@ -2394,10 +2394,9 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
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* non-cacheable as well.
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*/
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shr = tmp & GITS_BASER_SHAREABILITY_MASK;
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if (!shr) {
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if (!shr)
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cache = GITS_BASER_nC;
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gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
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}
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goto retry_baser;
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}
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@ -2609,6 +2608,11 @@ static int its_alloc_tables(struct its_node *its)
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/* erratum 24313: ignore memory access type */
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cache = GITS_BASER_nCnB;
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if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) {
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cache = GITS_BASER_nC;
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shr = 0;
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}
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for (i = 0; i < GITS_BASER_NR_REGS; i++) {
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struct its_baser *baser = its->tables + i;
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u64 val = its_read_baser(its, baser);
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