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drm/i915/icl: Update subslice define for ICL 11
ICL 11 has a greater number of maximum subslices. This patch reflects this. v2: GEN11 updates to MCR_SELECTOR (Oscar) v3: Copypasta error in the new defines (Lionel) Bspec: 21139 BSpec: 21108 Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com> (v1) Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v1) Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180316121456.11577-3-mika.kuoppala@linux.intel.com Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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3 changed files with 23 additions and 5 deletions
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@ -2151,6 +2151,10 @@ enum i915_power_well_id {
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#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
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#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
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#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
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#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
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#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
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#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
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#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
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#define RING_IPEIR(base) _MMIO((base)+0x64)
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#define RING_IPEHR(base) _MMIO((base)+0x68)
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/*
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@ -800,10 +800,24 @@ static inline uint32_t
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read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
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int subslice, i915_reg_t reg)
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{
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uint32_t mcr_slice_subslice_mask;
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uint32_t mcr_slice_subslice_select;
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uint32_t mcr;
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uint32_t ret;
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enum forcewake_domains fw_domains;
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if (INTEL_GEN(dev_priv) >= 11) {
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mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
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GEN11_MCR_SUBSLICE_MASK;
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mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
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GEN11_MCR_SUBSLICE(subslice);
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} else {
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mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
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GEN8_MCR_SUBSLICE_MASK;
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mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
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GEN8_MCR_SUBSLICE(subslice);
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}
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fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
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FW_REG_READ);
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fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
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@ -818,14 +832,14 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
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* The HW expects the slice and sublice selectors to be reset to 0
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* after reading out the registers.
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*/
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WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
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mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
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mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
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WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
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mcr &= ~mcr_slice_subslice_mask;
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mcr |= mcr_slice_subslice_select;
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I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
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ret = I915_READ_FW(reg);
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mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
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mcr &= ~mcr_slice_subslice_mask;
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I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
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intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
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@ -86,7 +86,7 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
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}
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#define I915_MAX_SLICES 3
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#define I915_MAX_SUBSLICES 3
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#define I915_MAX_SUBSLICES 8
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#define instdone_slice_mask(dev_priv__) \
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(INTEL_GEN(dev_priv__) == 7 ? \
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