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x86/intel_rdt: Move CBM specific data into a struct
Memory bandwidth allocation requires different information than cache allocation. To avoid a lump of data in struct rdt_resource, move all cache related information into a seperate structure and add that to struct rdt_resource. Sanitize the data types while at it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: ravi.v.shankar@intel.com Cc: tony.luck@intel.com Cc: fenghua.yu@intel.com Cc: vikas.shivappa@intel.com
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2545e9f51e
commit
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4 changed files with 83 additions and 65 deletions
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@ -73,37 +73,46 @@ struct rftype {
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char *buf, size_t nbytes, loff_t off);
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};
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/**
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* struct rdt_cache - Cache allocation related data
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* @cbm_len: Length of the cache bit mask
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* @min_cbm_bits: Minimum number of consecutive bits to be set
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* @cbm_idx_mult: Multiplier of CBM index
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* @cbm_idx_offset: Offset of CBM index. CBM index is computed by:
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* closid * cbm_idx_multi + cbm_idx_offset
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* in a cache bit mask
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*/
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struct rdt_cache {
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unsigned int cbm_len;
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unsigned int min_cbm_bits;
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unsigned int cbm_idx_mult;
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unsigned int cbm_idx_offset;
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};
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/**
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* struct rdt_resource - attributes of an RDT resource
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* @enabled: Is this feature enabled on this machine
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* @capable: Is this feature available on this machine
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* @name: Name to use in "schemata" file
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* @num_closid: Number of CLOSIDs available
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* @default_ctrl: Specifies default cache cbm or mem b/w percent.
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* @data_width: Character width of data when displaying
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* @min_cbm_bits: Minimum number of consecutive bits to be set
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* in a cache bit mask
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* @domains: All domains for this resource
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* @msr_base: Base MSR address for CBMs
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* @cache_level: Which cache level defines scope of this domain
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* @cbm_idx_multi: Multiplier of CBM index
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* @cbm_idx_offset: Offset of CBM index. CBM index is computed by:
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* closid * cbm_idx_multi + cbm_idx_offset
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* @enabled: Is this feature enabled on this machine
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* @capable: Is this feature available on this machine
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* @name: Name to use in "schemata" file
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* @num_closid: Number of CLOSIDs available
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* @cache_level: Which cache level defines scope of this resource
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* @default_ctrl: Specifies default cache cbm or memory B/W percent.
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* @msr_base: Base MSR address for CBMs
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* @data_width: Character width of data when displaying
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* @domains: All domains for this resource
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* @cache: Cache allocation related data
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*/
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struct rdt_resource {
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bool enabled;
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bool capable;
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char *name;
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int num_closid;
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int cbm_len;
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int min_cbm_bits;
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int cache_level;
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u32 default_ctrl;
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unsigned int msr_base;
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int data_width;
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struct list_head domains;
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int msr_base;
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int cache_level;
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int cbm_idx_multi;
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int cbm_idx_offset;
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struct rdt_cache cache;
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};
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/**
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@ -37,56 +37,64 @@ DEFINE_MUTEX(rdtgroup_mutex);
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DEFINE_PER_CPU_READ_MOSTLY(int, cpu_closid);
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#define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
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/*
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* Used to store the max resource name width and max resource data width
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* to display the schemata in a tabular format
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*/
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int max_name_width, max_data_width;
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#define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
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struct rdt_resource rdt_resources_all[] = {
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{
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.name = "L3",
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.domains = domain_init(RDT_RESOURCE_L3),
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.msr_base = IA32_L3_CBM_BASE,
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.min_cbm_bits = 1,
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.cache_level = 3,
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.cbm_idx_multi = 1,
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.cbm_idx_offset = 0
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.name = "L3",
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.domains = domain_init(RDT_RESOURCE_L3),
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.msr_base = IA32_L3_CBM_BASE,
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.cache_level = 3,
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.cache = {
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.min_cbm_bits = 1,
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.cbm_idx_mult = 1,
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.cbm_idx_offset = 0,
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},
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},
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{
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.name = "L3DATA",
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.domains = domain_init(RDT_RESOURCE_L3DATA),
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.msr_base = IA32_L3_CBM_BASE,
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.min_cbm_bits = 1,
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.cache_level = 3,
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.cbm_idx_multi = 2,
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.cbm_idx_offset = 0
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.name = "L3DATA",
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.domains = domain_init(RDT_RESOURCE_L3DATA),
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.msr_base = IA32_L3_CBM_BASE,
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.cache_level = 3,
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.cache = {
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.min_cbm_bits = 1,
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.cbm_idx_mult = 2,
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.cbm_idx_offset = 0,
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},
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},
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{
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.name = "L3CODE",
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.domains = domain_init(RDT_RESOURCE_L3CODE),
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.msr_base = IA32_L3_CBM_BASE,
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.min_cbm_bits = 1,
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.cache_level = 3,
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.cbm_idx_multi = 2,
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.cbm_idx_offset = 1
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.name = "L3CODE",
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.domains = domain_init(RDT_RESOURCE_L3CODE),
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.msr_base = IA32_L3_CBM_BASE,
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.cache_level = 3,
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.cache = {
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.min_cbm_bits = 1,
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.cbm_idx_mult = 2,
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.cbm_idx_offset = 1,
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},
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},
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{
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.name = "L2",
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.domains = domain_init(RDT_RESOURCE_L2),
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.msr_base = IA32_L2_CBM_BASE,
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.min_cbm_bits = 1,
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.cache_level = 2,
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.cbm_idx_multi = 1,
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.cbm_idx_offset = 0
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.name = "L2",
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.domains = domain_init(RDT_RESOURCE_L2),
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.msr_base = IA32_L2_CBM_BASE,
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.cache_level = 2,
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.cache = {
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.min_cbm_bits = 1,
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.cbm_idx_mult = 1,
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.cbm_idx_offset = 0,
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},
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},
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};
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static int cbm_idx(struct rdt_resource *r, int closid)
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static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
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{
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return closid * r->cbm_idx_multi + r->cbm_idx_offset;
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return closid * r->cache.cbm_idx_mult + r->cache.cbm_idx_offset;
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}
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/*
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@ -124,9 +132,9 @@ static inline bool cache_alloc_hsw_probe(void)
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return false;
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r->num_closid = 4;
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r->cbm_len = 20;
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r->default_ctrl = max_cbm;
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r->min_cbm_bits = 2;
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r->cache.cbm_len = 20;
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r->cache.min_cbm_bits = 2;
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r->capable = true;
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r->enabled = true;
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@ -144,9 +152,9 @@ static void rdt_get_cache_config(int idx, struct rdt_resource *r)
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cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
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r->num_closid = edx.split.cos_max + 1;
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r->cbm_len = eax.split.cbm_len + 1;
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r->cache.cbm_len = eax.split.cbm_len + 1;
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r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
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r->data_width = (r->cbm_len + 3) / 4;
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r->data_width = (r->cache.cbm_len + 3) / 4;
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r->capable = true;
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r->enabled = true;
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}
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@ -157,9 +165,9 @@ static void rdt_get_cdp_l3_config(int type)
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struct rdt_resource *r = &rdt_resources_all[type];
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r->num_closid = r_l3->num_closid / 2;
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r->cbm_len = r_l3->cbm_len;
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r->cache.cbm_len = r_l3->cache.cbm_len;
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r->default_ctrl = r_l3->default_ctrl;
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r->data_width = (r->cbm_len + 3) / 4;
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r->data_width = (r->cache.cbm_len + 3) / 4;
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r->capable = true;
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/*
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* By default, CDP is disabled. CDP can be enabled by mount parameter
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@ -200,7 +208,7 @@ void rdt_ctrl_update(void *arg)
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found:
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for (i = m->low; i < m->high; i++) {
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int idx = cbm_idx(r, i);
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unsigned int idx = cbm_idx(r, i);
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wrmsrl(r->msr_base + idx, d->ctrl_val[i]);
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}
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@ -282,7 +290,7 @@ static void domain_add_cpu(int cpu, struct rdt_resource *r)
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}
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for (i = 0; i < r->num_closid; i++) {
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int idx = cbm_idx(r, i);
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unsigned int idx = cbm_idx(r, i);
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d->ctrl_val[i] = r->default_ctrl;
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wrmsrl(r->msr_base + idx, d->ctrl_val[i]);
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@ -534,7 +534,7 @@ static int rdt_min_cbm_bits_show(struct kernfs_open_file *of,
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{
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struct rdt_resource *r = of->kn->parent->priv;
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seq_printf(seq, "%d\n", r->min_cbm_bits);
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seq_printf(seq, "%u\n", r->cache.min_cbm_bits);
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return 0;
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}
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@ -37,17 +37,18 @@
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static bool cbm_validate(unsigned long var, struct rdt_resource *r)
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{
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unsigned long first_bit, zero_bit;
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unsigned int cbm_len = r->cache.cbm_len;
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if (var == 0 || var > r->default_ctrl)
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return false;
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first_bit = find_first_bit(&var, r->cbm_len);
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zero_bit = find_next_zero_bit(&var, r->cbm_len, first_bit);
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first_bit = find_first_bit(&var, cbm_len);
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zero_bit = find_next_zero_bit(&var, cbm_len, first_bit);
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if (find_next_bit(&var, r->cbm_len, zero_bit) < r->cbm_len)
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if (find_next_bit(&var, cbm_len, zero_bit) < cbm_len)
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return false;
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if ((zero_bit - first_bit) < r->min_cbm_bits)
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if ((zero_bit - first_bit) < r->cache.min_cbm_bits)
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return false;
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return true;
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}
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