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ARM: 5935/1: [U300] Fix the DMA configuration
This fixes a few bugs in the DMA configuration for the COH 901 318 DMA engine used in U300. It also removes the directional parameter for each channel: separate DMA engine patches (submitted to the DMA engine maintainer) switches that mechanism over to using dynamic configuration of this, to handle bidirectional DMA channels. Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
59778fb6c4
commit
d40956665d
1 changed files with 4 additions and 18 deletions
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@ -475,7 +475,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -528,7 +527,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -582,7 +580,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -635,7 +632,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -706,7 +702,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -746,7 +741,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -799,7 +793,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -852,7 +845,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -905,7 +897,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -964,7 +955,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MMCSD_BASE + 0x080,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -974,8 +964,8 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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@ -986,7 +976,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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@ -996,7 +986,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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@ -1039,7 +1029,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 1,
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.dev_addr = U300_PCM_I2S0_BASE + 0x14,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -1092,7 +1081,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 1,
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.dev_addr = U300_PCM_I2S0_BASE + 0x10,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -1145,7 +1133,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 1,
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.dev_addr = U300_PCM_I2S1_BASE + 0x14,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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@ -1198,7 +1185,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 1,
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.dev_addr = U300_PCM_I2S1_BASE + 0x10,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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