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drm/amdgpu: add some [WR]REG32_SDMA macros to sdma_v4_0.c
Significantly shortens the code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
Alex Deucher
parent
998d3fd4f8
commit
d425e7d8de
1 changed files with 63 additions and 63 deletions
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@ -54,6 +54,11 @@ MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
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#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
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#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
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#define WREG32_SDMA(instance, offset, value) \
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WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
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#define RREG32_SDMA(instance, offset) \
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RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
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static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
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static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
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static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
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@ -369,8 +374,8 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
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} else {
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u32 lowbit, highbit;
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lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
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highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
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lowbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR) >> 2;
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highbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI) >> 2;
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DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
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ring->me, highbit, lowbit);
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@ -417,8 +422,10 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
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lower_32_bits(ring->wptr << 2),
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ring->me,
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upper_32_bits(ring->wptr << 2));
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WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
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WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
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WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
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lower_32_bits(ring->wptr << 2));
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WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
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upper_32_bits(ring->wptr << 2));
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}
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}
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@ -568,12 +575,12 @@ static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
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amdgpu_ttm_set_buffer_funcs_status(adev, false);
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for (i = 0; i < adev->sdma.num_instances; i++) {
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rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
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rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
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WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
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ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
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}
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sdma0->ready = false;
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@ -630,18 +637,15 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
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}
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for (i = 0; i < adev->sdma.num_instances; i++) {
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f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
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f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
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f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
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AUTO_CTXSW_ENABLE, enable ? 1 : 0);
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if (enable && amdgpu_sdma_phase_quantum) {
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
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phase_quantum);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
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phase_quantum);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
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phase_quantum);
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WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
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WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
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WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
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}
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
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WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
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}
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}
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@ -665,9 +669,9 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
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}
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for (i = 0; i < adev->sdma.num_instances; i++) {
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f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
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f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
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f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
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WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
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}
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}
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@ -694,39 +698,39 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
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/* Set ring buffer size in dwords */
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rb_bufsz = order_base_2(ring->ring_size / 4);
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rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
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rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
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#ifdef __BIG_ENDIAN
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
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RPTR_WRITEBACK_SWAP_ENABLE, 1);
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#endif
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
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/* set the wb address whether it's enabled or not */
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
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WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
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upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
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WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
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lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
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ring->wptr = 0;
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/* before programing wptr to a less value, need set minor_ptr_update first */
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
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WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
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doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
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doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
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doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
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doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
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if (ring->use_doorbell) {
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doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
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@ -735,40 +739,40 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
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} else {
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doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
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}
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
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WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
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WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
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adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
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ring->doorbell_index);
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sdma_v4_0_ring_set_wptr(ring);
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/* set minor_ptr_update to 0 after wptr programed */
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
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WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
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/* setup the wptr shadow polling */
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wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
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lower_32_bits(wptr_gpu_addr));
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
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upper_32_bits(wptr_gpu_addr));
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wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
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WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
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lower_32_bits(wptr_gpu_addr));
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WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
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upper_32_bits(wptr_gpu_addr));
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wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
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if (amdgpu_sriov_vf(adev))
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wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
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else
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wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
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/* enable DMA RB */
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
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ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
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ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
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#ifdef __BIG_ENDIAN
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
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#endif
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/* enable DMA IBs */
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
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ring->ready = true;
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}
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@ -881,12 +885,14 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
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(adev->sdma.instance[i].fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
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WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
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for (j = 0; j < fw_size; j++)
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
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WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
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le32_to_cpup(fw_data++));
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
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WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
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adev->sdma.instance[i].fw_version);
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}
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return 0;
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@ -926,22 +932,19 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
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for (i = 0; i < adev->sdma.num_instances; i++) {
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uint32_t temp;
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WREG32(sdma_v4_0_get_reg_offset(adev, i,
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mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
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WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
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sdma_v4_0_gfx_resume(adev, i);
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/* set utc l1 enable flag always to 1 */
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temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
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temp = RREG32_SDMA(i, mmSDMA0_CNTL);
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temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
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WREG32_SDMA(i, mmSDMA0_CNTL, temp);
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if (!amdgpu_sriov_vf(adev)) {
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/* unhalt engine */
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temp = RREG32(sdma_v4_0_get_reg_offset(adev, i,
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mmSDMA0_F32_CNTL));
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temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
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temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i,
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mmSDMA0_F32_CNTL), temp);
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WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
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}
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}
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@ -1410,7 +1413,7 @@ static bool sdma_v4_0_is_idle(void *handle)
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u32 i;
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for (i = 0; i < adev->sdma.num_instances; i++) {
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u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
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u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
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if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
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return false;
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@ -1426,8 +1429,8 @@ static int sdma_v4_0_wait_for_idle(void *handle)
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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for (i = 0; i < adev->usec_timeout; i++) {
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sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
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sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
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sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG);
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sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG);
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if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
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return 0;
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@ -1448,16 +1451,13 @@ static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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unsigned int instance = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 0 : 1;
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u32 sdma_cntl;
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u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
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sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
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sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
|
||||
|
||||
sdma_cntl = RREG32(reg_offset);
|
||||
sdma_cntl = RREG32_SDMA(instance, mmSDMA0_CNTL);
|
||||
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
|
||||
state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
|
||||
WREG32(reg_offset, sdma_cntl);
|
||||
WREG32_SDMA(instance, mmSDMA0_CNTL, sdma_cntl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue