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qed: reformat public_port::transceiver_data a bit
Prior to adding new bitfields, reformat the existing ones from spaces to tabs, and unify all hex values to lowercase. Signed-off-by: Alexander Lobakin <alobakin@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 55 additions and 53 deletions
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@ -11973,59 +11973,61 @@ struct public_port {
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struct dcbx_mib operational_dcbx_mib;
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struct dcbx_mib operational_dcbx_mib;
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u32 reserved[2];
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u32 reserved[2];
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u32 transceiver_data;
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#define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
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u32 transceiver_data;
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#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
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#define ETH_TRANSCEIVER_STATE_MASK 0x000000ff
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#define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
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#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
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#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
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#define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
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#define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
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#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
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#define ETH_TRANSCEIVER_STATE_VALID 0x00000003
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#define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
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#define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
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#define ETH_TRANSCEIVER_STATE_VALID 0x00000003
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#define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00
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#define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
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#define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
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#define ETH_TRANSCEIVER_TYPE_MASK 0x0000ff00
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#define ETH_TRANSCEIVER_TYPE_NONE 0x00
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#define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
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#define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xFF
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#define ETH_TRANSCEIVER_TYPE_NONE 0x00
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#define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
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#define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xff
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#define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
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#define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
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#define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
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#define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
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#define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
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#define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
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#define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
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#define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
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#define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
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#define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
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#define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
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#define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
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#define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
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#define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
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#define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
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#define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
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#define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
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#define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
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#define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
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#define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
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#define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
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#define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
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#define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
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#define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
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#define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
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#define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
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#define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
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#define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
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#define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
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#define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
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#define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
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#define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
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#define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
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#define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
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#define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
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#define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
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#define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
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#define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
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#define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
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#define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
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#define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
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#define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
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#define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
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#define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
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#define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
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#define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
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#define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
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#define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
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#define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
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#define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
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#define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
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#define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
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#define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
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#define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
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#define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
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#define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
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#define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
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#define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
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#define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
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#define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
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#define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
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#define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
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#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
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#define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
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#define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
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#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
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#define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
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#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
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u32 wol_info;
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u32 wol_info;
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u32 wol_pkt_len;
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u32 wol_pkt_len;
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u32 wol_pkt_details;
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u32 wol_pkt_details;
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