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drm/amd/display: intermittent underflow observed when PIP is toggled in Full screen

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[Why]
The MPCC may change and request data when the pipes are switching from 2
to 1 or 1 to 2. During the switch there is a possibility of underflow
and flicker/missing data.

[How]
During VBlank the MPCC won't request data. The trick is to delay and
wait on VBlank, ONLY when pipes are either turning on or off, right
before MPCC is reset for the pipes.

Signed-off-by: Tashfique Abdullah <tabdullah@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tashfique Abdullah 2020-11-04 18:51:53 -05:00 committed by Alex Deucher
parent 96879ad3e4
commit d4930b7aae
1 changed files with 9 additions and 0 deletions
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9
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
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@ -1695,6 +1695,15 @@ void dcn20_program_front_end_for_ctx(
&& context->res_ctx.pipe_ctx[i].stream)
hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
/* wait for outstanding pending changes before adding or removing planes */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||
context->res_ctx.pipe_ctx[i].update_flags.bits.enable) {
dc->hwss.wait_for_pending_cleared(dc, context);
break;
}
}
/* Disconnect mpcc */
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable