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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm/amdgpu/jpeg: add JPEG multiple AIDs support
Add JPEG multiple AIDs support. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu
Alex Deucher
parent
2e10ced47f
commit
d4ad24a0b7
1 changed files with 214 additions and 140 deletions
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@ -63,6 +63,8 @@ static int jpeg_v4_0_3_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS;
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jpeg_v4_0_3_set_dec_ring_funcs(adev);
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jpeg_v4_0_3_set_irq_funcs(adev);
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@ -80,12 +82,12 @@ static int jpeg_v4_0_3_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_ring *ring;
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int i, r;
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int i, j, r;
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for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
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/* JPEG TRAP */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
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amdgpu_ih_srcid_jpeg[i], &adev->jpeg.inst->irq);
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amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);
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if (r)
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return r;
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}
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@ -98,22 +100,27 @@ static int jpeg_v4_0_3_sw_init(void *handle)
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if (r)
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return r;
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for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
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ring = &adev->jpeg.inst->ring_dec[i];
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ring->use_doorbell = true;
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ring->vm_hub = AMDGPU_MMHUB0(0);
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ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
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sprintf(ring->name, "jpeg_dec_%d", i);
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r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
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AMDGPU_RING_PRIO_DEFAULT, NULL);
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if (r)
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return r;
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
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ring = &adev->jpeg.inst[i].ring_dec[j];
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ring->use_doorbell = true;
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ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
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ring->doorbell_index =
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + j + 9 * i;
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sprintf(ring->name, "jpeg_dec_%d.%d", i, j);
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r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
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AMDGPU_RING_PRIO_DEFAULT, NULL);
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if (r)
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return r;
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adev->jpeg.internal.jpeg_pitch[i] =
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regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET;
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adev->jpeg.inst->external.jpeg_pitch[i] =
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SOC15_REG_OFFSET1(JPEG, 0, regUVD_JRBC0_UVD_JRBC_SCRATCH0,
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(i?(0x40 * i - 0xc80):0));
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adev->jpeg.internal.jpeg_pitch[j] =
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regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET;
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adev->jpeg.inst[i].external.jpeg_pitch[j] =
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SOC15_REG_OFFSET1(JPEG, i, regUVD_JRBC0_UVD_JRBC_SCRATCH0,
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(j?(0x40 * j - 0xc80):0));
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}
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}
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return 0;
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@ -149,22 +156,30 @@ static int jpeg_v4_0_3_sw_fini(void *handle)
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static int jpeg_v4_0_3_hw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
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int i, r;
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struct amdgpu_ring *ring;
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int i, j, r;
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adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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ring = adev->jpeg.inst[i].ring_dec;
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for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
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ring = &adev->jpeg.inst->ring_dec[i];
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if (ring->use_doorbell)
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WREG32_SOC15_OFFSET(VCN, 0, regVCN_JPEG_DB_CTRL,
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(ring->pipe?(ring->pipe - 0x15):0),
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ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
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VCN_JPEG_DB_CTRL__EN_MASK);
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r = amdgpu_ring_test_helper(ring);
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if (r)
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return r;
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adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * i,
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adev->jpeg.inst[i].aid_id);
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
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ring = &adev->jpeg.inst[i].ring_dec[j];
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if (ring->use_doorbell)
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WREG32_SOC15_OFFSET(VCN, i, regVCN_JPEG_DB_CTRL,
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(ring->pipe?(ring->pipe - 0x15):0),
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ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
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VCN_JPEG_DB_CTRL__EN_MASK);
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r = amdgpu_ring_test_helper(ring);
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if (r)
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return r;
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}
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}
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DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
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@ -233,48 +248,52 @@ static int jpeg_v4_0_3_resume(void *handle)
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return r;
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}
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static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev)
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static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx)
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{
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uint32_t data;
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int i;
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data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
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data = RREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
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data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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else
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data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1));
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} else {
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data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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}
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data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
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WREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_CTRL, data);
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data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
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data = RREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_GATE);
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data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK);
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for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)
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data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i);
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WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
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WREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_GATE, data);
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}
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static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev)
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static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx)
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{
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uint32_t data;
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int i;
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data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
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data = RREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
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data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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else
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data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1);
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} else {
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data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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}
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data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
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WREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_CTRL, data);
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data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
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data = RREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_GATE);
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data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK);
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for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)
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data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i);
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WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
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WREG32_SOC15(JPEG, inst_idx, regJPEG_CGC_GATE, data);
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}
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/**
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@ -286,58 +305,63 @@ static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev)
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*/
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static int jpeg_v4_0_3_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
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int i;
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struct amdgpu_ring *ring;
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int i, j;
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WREG32_SOC15(JPEG, 0, regUVD_PGFSM_CONFIG,
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1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
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SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS,
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UVD_PGFSM_STATUS__UVDJ_PWR_ON <<
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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WREG32_SOC15(JPEG, i, regUVD_PGFSM_CONFIG,
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1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
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SOC15_WAIT_ON_RREG(JPEG, i, regUVD_PGFSM_STATUS,
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UVD_PGFSM_STATUS__UVDJ_PWR_ON <<
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
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/* disable anti hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
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~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
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/* disable anti hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_POWER_STATUS), 0,
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~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
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/* JPEG disable CGC */
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jpeg_v4_0_3_disable_clock_gating(adev);
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/* JPEG disable CGC */
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jpeg_v4_0_3_disable_clock_gating(adev, i);
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/* MJPEG global tiling registers */
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WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX8_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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/* MJPEG global tiling registers */
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WREG32_SOC15(JPEG, i, regJPEG_DEC_GFX8_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(JPEG, i, regJPEG_DEC_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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/* enable JMI channel */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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/* enable JMI channel */
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WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), 0,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
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unsigned int reg_offset = (i?(0x40 * i - 0xc80):0);
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
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unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
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ring = &adev->jpeg.inst->ring_dec[i];
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ring = &adev->jpeg.inst[i].ring_dec[j];
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/* enable System Interrupt for JRBC */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
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JPEG_SYS_INT_EN__DJRBC0_MASK << i,
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~(JPEG_SYS_INT_EN__DJRBC0_MASK << i));
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/* enable System Interrupt for JRBC */
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WREG32_P(SOC15_REG_OFFSET(JPEG, i, regJPEG_SYS_INT_EN),
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JPEG_SYS_INT_EN__DJRBC0_MASK << j,
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~(JPEG_SYS_INT_EN__DJRBC0_MASK << j));
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WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, reg_offset, 0);
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WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_CNTL, reg_offset,
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(0x00000001L | 0x00000002L));
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WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW,
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reg_offset, lower_32_bits(ring->gpu_addr));
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WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
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reg_offset, upper_32_bits(ring->gpu_addr));
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WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR, reg_offset, 0);
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WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR, reg_offset, 0);
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WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_CNTL, reg_offset,
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0x00000002L);
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WREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE, reg_offset,
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ring->ring_size / 4);
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ring->wptr = RREG32_SOC15_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR,
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reg_offset);
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WREG32_SOC15_OFFSET(JPEG, i,
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regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, reg_offset, 0);
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WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_CNTL, reg_offset,
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(0x00000001L | 0x00000002L));
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WREG32_SOC15_OFFSET(JPEG, i, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW,
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reg_offset, lower_32_bits(ring->gpu_addr));
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WREG32_SOC15_OFFSET(JPEG, i, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
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reg_offset, upper_32_bits(ring->gpu_addr));
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WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_RPTR, reg_offset, 0);
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WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_WPTR, reg_offset, 0);
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WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_CNTL, reg_offset,
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0x00000002L);
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WREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_SIZE, reg_offset,
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ring->ring_size / 4);
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ring->wptr = RREG32_SOC15_OFFSET(JPEG, i, regUVD_JRBC0_UVD_JRBC_RB_WPTR,
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reg_offset);
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}
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}
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return 0;
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@ -352,24 +376,31 @@ static int jpeg_v4_0_3_start(struct amdgpu_device *adev)
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*/
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static int jpeg_v4_0_3_stop(struct amdgpu_device *adev)
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{
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/* reset JMI */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
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UVD_JMI_CNTL__SOFT_RESET_MASK,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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int i;
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jpeg_v4_0_3_enable_clock_gating(adev);
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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/* enable anti hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
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UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
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~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
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/* reset JMI */
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WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL),
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UVD_JMI_CNTL__SOFT_RESET_MASK,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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WREG32_SOC15(JPEG, 0, regUVD_PGFSM_CONFIG,
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2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
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SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS,
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UVD_PGFSM_STATUS__UVDJ_PWR_OFF <<
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
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UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
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jpeg_v4_0_3_enable_clock_gating(adev, i);
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/* enable anti hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_POWER_STATUS),
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UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
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~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
|
||||
|
||||
WREG32_SOC15(JPEG, i, regUVD_PGFSM_CONFIG,
|
||||
2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
|
||||
SOC15_WAIT_ON_RREG(JPEG, i, regUVD_PGFSM_STATUS,
|
||||
UVD_PGFSM_STATUS__UVDJ_PWR_OFF <<
|
||||
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
|
||||
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -502,10 +533,28 @@ static void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
|
|||
0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
|
||||
amdgpu_ring_write(ring, 0);
|
||||
|
||||
if (ring->adev->jpeg.inst[ring->me].aid_id) {
|
||||
amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
|
||||
0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
|
||||
amdgpu_ring_write(ring, 0x4);
|
||||
} else {
|
||||
amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
|
||||
amdgpu_ring_write(ring, 0);
|
||||
}
|
||||
|
||||
amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
|
||||
0, 0, PACKETJ_TYPE0));
|
||||
amdgpu_ring_write(ring, 0x3fbc);
|
||||
|
||||
if (ring->adev->jpeg.inst[ring->me].aid_id) {
|
||||
amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
|
||||
0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
|
||||
amdgpu_ring_write(ring, 0x0);
|
||||
} else {
|
||||
amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
|
||||
amdgpu_ring_write(ring, 0);
|
||||
}
|
||||
|
||||
amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
|
||||
0, 0, PACKETJ_TYPE0));
|
||||
amdgpu_ring_write(ring, 0x1);
|
||||
|
|
@ -651,15 +700,19 @@ static bool jpeg_v4_0_3_is_idle(void *handle)
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
bool ret;
|
||||
int i;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
|
||||
unsigned int reg_offset = (i?(0x40 * i - 0xc80):0);
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
if (adev->jpeg.harvest_config & (1 << i))
|
||||
continue;
|
||||
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
|
||||
unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
|
||||
|
||||
ret &= ((RREG32_SOC15_OFFSET(JPEG, 0,
|
||||
regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset) &
|
||||
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
|
||||
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
|
||||
ret &= ((RREG32_SOC15_OFFSET(JPEG, i,
|
||||
regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset) &
|
||||
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
|
||||
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -669,17 +722,20 @@ static int jpeg_v4_0_3_wait_for_idle(void *handle)
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
int ret;
|
||||
int i;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
|
||||
unsigned int reg_offset = (i?(0x40 * i - 0xc80):0);
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
if (adev->jpeg.harvest_config & (1 << i))
|
||||
continue;
|
||||
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
|
||||
unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
|
||||
|
||||
ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, 0,
|
||||
regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset,
|
||||
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
|
||||
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
|
||||
ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, i,
|
||||
regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset,
|
||||
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
|
||||
UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -688,15 +744,19 @@ static int jpeg_v4_0_3_set_clockgating_state(void *handle,
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
|
||||
int i;
|
||||
|
||||
if (enable) {
|
||||
if (!jpeg_v4_0_3_is_idle(handle))
|
||||
return -EBUSY;
|
||||
jpeg_v4_0_3_enable_clock_gating(adev);
|
||||
} else {
|
||||
jpeg_v4_0_3_disable_clock_gating(adev);
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
if (adev->jpeg.harvest_config & (1 << i))
|
||||
continue;
|
||||
if (enable) {
|
||||
if (!jpeg_v4_0_3_is_idle(handle))
|
||||
return -EBUSY;
|
||||
jpeg_v4_0_3_enable_clock_gating(adev, i);
|
||||
} else {
|
||||
jpeg_v4_0_3_disable_clock_gating(adev, i);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -732,32 +792,35 @@ static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev,
|
|||
struct amdgpu_irq_src *source,
|
||||
struct amdgpu_iv_entry *entry)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
i = node_id_to_phys_map[entry->node_id];
|
||||
DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n");
|
||||
|
||||
switch (entry->src_id) {
|
||||
case VCN_4_0__SRCID__JPEG_DECODE:
|
||||
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[0]);
|
||||
amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[0]);
|
||||
break;
|
||||
case VCN_4_0__SRCID__JPEG1_DECODE:
|
||||
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[1]);
|
||||
amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[1]);
|
||||
break;
|
||||
case VCN_4_0__SRCID__JPEG2_DECODE:
|
||||
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[2]);
|
||||
amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[2]);
|
||||
break;
|
||||
case VCN_4_0__SRCID__JPEG3_DECODE:
|
||||
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[3]);
|
||||
amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[3]);
|
||||
break;
|
||||
case VCN_4_0__SRCID__JPEG4_DECODE:
|
||||
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[4]);
|
||||
amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[4]);
|
||||
break;
|
||||
case VCN_4_0__SRCID__JPEG5_DECODE:
|
||||
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[5]);
|
||||
amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[5]);
|
||||
break;
|
||||
case VCN_4_0__SRCID__JPEG6_DECODE:
|
||||
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[6]);
|
||||
amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[6]);
|
||||
break;
|
||||
case VCN_4_0__SRCID__JPEG7_DECODE:
|
||||
amdgpu_fence_process(&adev->jpeg.inst->ring_dec[7]);
|
||||
amdgpu_fence_process(&adev->jpeg.inst[i].ring_dec[7]);
|
||||
break;
|
||||
default:
|
||||
DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
|
||||
|
|
@ -798,7 +861,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
|
|||
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
|
||||
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
|
||||
8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */
|
||||
18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */
|
||||
22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */
|
||||
8 + 16,
|
||||
.emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */
|
||||
.emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,
|
||||
|
|
@ -819,12 +882,17 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
|
|||
|
||||
static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
int i;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
|
||||
adev->jpeg.inst->ring_dec[i].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs;
|
||||
adev->jpeg.inst->ring_dec[i].me = 0;
|
||||
adev->jpeg.inst->ring_dec[i].pipe = i;
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
if (adev->jpeg.harvest_config & (1 << i))
|
||||
continue;
|
||||
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
|
||||
adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs;
|
||||
adev->jpeg.inst[i].ring_dec[j].me = i;
|
||||
adev->jpeg.inst[i].ring_dec[j].pipe = j;
|
||||
}
|
||||
adev->jpeg.inst[i].aid_id = i / adev->jpeg.num_inst_per_aid;
|
||||
}
|
||||
DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
|
||||
}
|
||||
|
|
@ -836,7 +904,13 @@ static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = {
|
|||
|
||||
static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
adev->jpeg.inst->irq.num_types = adev->jpeg.num_jpeg_rings;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
||||
if (adev->jpeg.harvest_config & (1 << i))
|
||||
continue;
|
||||
adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;
|
||||
}
|
||||
adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue