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Merge branches 'pnp' and 'acpi-hotplug'
* pnp: PNP: Work around BIOS defects in Intel MCH area reporting * acpi-hotplug: ACPI / notify: Do not block unknown type notifications in root handler
This commit is contained in:
commit
d4c9c8a09c
2 changed files with 81 additions and 3 deletions
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@ -380,9 +380,8 @@ static void acpi_bus_notify(acpi_handle handle, u32 type, void *data)
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break;
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default:
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acpi_handle_warn(handle, "Unsupported event type 0x%x\n", type);
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ost_code = ACPI_OST_SC_UNRECOGNIZED_NOTIFY;
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goto err;
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acpi_handle_debug(handle, "Unknown event type 0x%x\n", type);
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break;
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}
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adev = acpi_bus_get_acpi_device(handle);
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@ -15,6 +15,7 @@
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/pnp.h>
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@ -334,6 +335,81 @@ static void quirk_amd_mmconfig_area(struct pnp_dev *dev)
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}
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#endif
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#ifdef CONFIG_X86
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/* Device IDs of parts that have 32KB MCH space */
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static const unsigned int mch_quirk_devices[] = {
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0x0154, /* Ivy Bridge */
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0x0c00, /* Haswell */
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};
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static struct pci_dev *get_intel_host(void)
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{
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int i;
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struct pci_dev *host;
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for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) {
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host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i],
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NULL);
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if (host)
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return host;
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}
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return NULL;
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}
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static void quirk_intel_mch(struct pnp_dev *dev)
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{
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struct pci_dev *host;
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u32 addr_lo, addr_hi;
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struct pci_bus_region region;
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struct resource mch;
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struct pnp_resource *pnp_res;
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struct resource *res;
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host = get_intel_host();
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if (!host)
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return;
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/*
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* MCHBAR is not an architected PCI BAR, so MCH space is usually
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* reported as a PNP0C02 resource. The MCH space was originally
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* 16KB, but is 32KB in newer parts. Some BIOSes still report a
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* PNP0C02 resource that is only 16KB, which means the rest of the
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* MCH space is consumed but unreported.
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*/
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/*
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* Read MCHBAR for Host Member Mapped Register Range Base
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* https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet
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* Sec 3.1.12.
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*/
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pci_read_config_dword(host, 0x48, &addr_lo);
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region.start = addr_lo & ~0x7fff;
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pci_read_config_dword(host, 0x4c, &addr_hi);
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region.start |= (u64) addr_hi << 32;
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region.end = region.start + 32*1024 - 1;
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memset(&mch, 0, sizeof(mch));
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mch.flags = IORESOURCE_MEM;
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pcibios_bus_to_resource(host->bus, &mch, ®ion);
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list_for_each_entry(pnp_res, &dev->resources, list) {
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res = &pnp_res->res;
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if (res->end < mch.start || res->start > mch.end)
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continue; /* no overlap */
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if (res->start == mch.start && res->end == mch.end)
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continue; /* exact match */
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dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n",
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res, pci_name(host), &mch);
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res->start = mch.start;
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res->end = mch.end;
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break;
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}
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pci_dev_put(host);
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}
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#endif
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/*
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* PnP Quirks
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* Cards or devices that need some tweaking due to incomplete resource info
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@ -363,6 +439,9 @@ static struct pnp_fixup pnp_fixups[] = {
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{"PNP0c02", quirk_system_pci_resources},
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#ifdef CONFIG_AMD_NB
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{"PNP0c01", quirk_amd_mmconfig_area},
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#endif
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#ifdef CONFIG_X86
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{"PNP0c02", quirk_intel_mch},
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#endif
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{""}
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};
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