ARC: mm: fix new code about cache aliasing
Manual/partial revert of 8690bbcf3b
("Introduce cpu_dcache_is_aliasing() across all architectures")
Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).
Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) [1] however recently that support was ripped out so VIPT aliasing
cache is not relevant to ARC anymore.
[1] http://lists.infradead.org/pipermail/linux-snps-arc/2023-February/006899.html
Acked-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
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@ -6,7 +6,6 @@
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config ARC
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def_bool y
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select ARC_TIMERS
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select ARCH_HAS_CPU_CACHE_ALIASING
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select ARCH_HAS_CACHE_LINE_SIZE
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select ARCH_HAS_DEBUG_VM_PGTABLE
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select ARCH_HAS_DMA_PREP_COHERENT
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@ -1,9 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ARC_CACHETYPE_H
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#define __ASM_ARC_CACHETYPE_H
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#include <linux/types.h>
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#define cpu_dcache_is_aliasing() true
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#endif
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