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drm/radeon/si: fix define for MC_SEQ_TRAIN_WAKEUP_CNTL
Typo in the register offset. Noticed-by: Sylvain BERTRAND <sylware@legeek.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -478,7 +478,7 @@
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#define STATE3_MASK (0x1f << 15)
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#define STATE3_SHIFT 15
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#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
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#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
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#define TRAIN_DONE_D0 (1 << 30)
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#define TRAIN_DONE_D1 (1 << 31)
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