drm/amdgpu/vpe: fix vpe dpm setup failed
The vpe dpm settings should be done before firmware is loaded. Otherwise, the frequency cannot be successfully raised. Signed-off-by: Peyton Lee <peytolee@amd.com> Reviewed-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
aebd3eb9d3
commit
d59198d2d0
|
@ -205,7 +205,7 @@ disable_dpm:
|
||||||
dpm_ctl &= 0xfffffffe; /* Disable DPM */
|
dpm_ctl &= 0xfffffffe; /* Disable DPM */
|
||||||
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
|
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
|
||||||
dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__);
|
dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__);
|
||||||
return 0;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)
|
int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)
|
||||||
|
|
|
@ -144,6 +144,12 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)
|
||||||
WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL), ret);
|
WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL), ret);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* setup collaborate mode */
|
||||||
|
vpe_v6_1_set_collaborate_mode(vpe, true);
|
||||||
|
/* setup DPM */
|
||||||
|
if (amdgpu_vpe_configure_dpm(vpe))
|
||||||
|
dev_warn(adev->dev, "VPE failed to enable DPM\n");
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* For VPE 6.1.1, still only need to add master's offset, and psp will apply it to slave as well.
|
* For VPE 6.1.1, still only need to add master's offset, and psp will apply it to slave as well.
|
||||||
* Here use instance 0 as master.
|
* Here use instance 0 as master.
|
||||||
|
@ -159,11 +165,7 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)
|
||||||
adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;
|
adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;
|
||||||
adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;
|
adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;
|
||||||
|
|
||||||
amdgpu_vpe_psp_update_sram(adev);
|
return amdgpu_vpe_psp_update_sram(adev);
|
||||||
vpe_v6_1_set_collaborate_mode(vpe, true);
|
|
||||||
amdgpu_vpe_configure_dpm(vpe);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;
|
vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;
|
||||||
|
@ -196,8 +198,6 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)
|
||||||
}
|
}
|
||||||
|
|
||||||
vpe_v6_1_halt(vpe, false);
|
vpe_v6_1_halt(vpe, false);
|
||||||
vpe_v6_1_set_collaborate_mode(vpe, true);
|
|
||||||
amdgpu_vpe_configure_dpm(vpe);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue