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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 05:44:11 +00:00
pinctrl: cherryview: Simplify code with cleanup helpers
Use macros defined in linux/cleanup.h to automate resource lifetime control in the driver. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This commit is contained in:
Andy Shevchenko
parent
d338655215
commit
d59b099c66
1 changed files with 46 additions and 90 deletions
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@ -12,6 +12,7 @@
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#include <linux/acpi.h>
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#include <linux/array_size.h>
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#include <linux/cleanup.h>
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#include <linux/dmi.h>
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#include <linux/gpio/driver.h>
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#include <linux/module.h>
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@ -626,15 +627,12 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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unsigned int offset)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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u32 ctrl0, ctrl1;
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raw_spin_lock_irqsave(&chv_lock, flags);
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ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
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ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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scoped_guard(raw_spinlock_irqsave, &chv_lock) {
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ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
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ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
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}
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if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
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seq_puts(s, "GPIO ");
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@ -666,17 +664,15 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct device *dev = pctrl->dev;
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const struct intel_pingroup *grp;
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unsigned long flags;
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int i;
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grp = &pctrl->soc->groups[group];
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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/* Check first that the pad is not locked */
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for (i = 0; i < grp->grp.npins; i++) {
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if (chv_pad_locked(pctrl, grp->grp.pins[i])) {
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]);
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return -EBUSY;
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}
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@ -716,8 +712,6 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
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invert_oe ? "" : "not ");
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}
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return 0;
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}
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@ -748,16 +742,14 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
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unsigned int offset)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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if (chv_pad_locked(pctrl, offset)) {
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value = chv_readl(pctrl, offset, CHV_PADCTRL0);
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if (!(value & CHV_PADCTRL0_GPIOEN)) {
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/* Locked so cannot enable */
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return -EBUSY;
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}
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} else {
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@ -792,8 +784,6 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
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chv_writel(pctrl, offset, CHV_PADCTRL0, value);
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}
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return 0;
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}
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@ -802,14 +792,13 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
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unsigned int offset)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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if (!chv_pad_locked(pctrl, offset))
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chv_gpio_clear_triggering(pctrl, offset);
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if (chv_pad_locked(pctrl, offset))
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return;
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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chv_gpio_clear_triggering(pctrl, offset);
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}
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static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
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@ -817,10 +806,9 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
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unsigned int offset, bool input)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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u32 ctrl0;
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
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if (input)
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@ -829,8 +817,6 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
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ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
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chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return 0;
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}
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@ -849,15 +835,14 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned long flags;
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u32 ctrl0, ctrl1;
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u16 arg = 0;
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u32 term;
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raw_spin_lock_irqsave(&chv_lock, flags);
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ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
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ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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scoped_guard(raw_spinlock_irqsave, &chv_lock) {
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ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
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ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
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}
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term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
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@ -932,10 +917,10 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
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enum pin_config_param param, u32 arg)
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{
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unsigned long flags;
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u32 ctrl0, pull;
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
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switch (param) {
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@ -958,7 +943,6 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
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pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
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break;
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default:
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return -EINVAL;
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}
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@ -976,7 +960,6 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
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pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
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break;
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default:
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return -EINVAL;
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}
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@ -984,12 +967,10 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
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break;
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default:
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return -EINVAL;
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}
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chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return 0;
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}
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@ -997,10 +978,10 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
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static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
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bool enable)
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{
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unsigned long flags;
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u32 ctrl1;
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
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if (enable)
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@ -1009,7 +990,6 @@ static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
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ctrl1 &= ~CHV_PADCTRL1_ODEN;
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chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return 0;
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}
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@ -1119,12 +1099,10 @@ static struct pinctrl_desc chv_pinctrl_desc = {
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static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
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unsigned long flags;
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u32 ctrl0, cfg;
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raw_spin_lock_irqsave(&chv_lock, flags);
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ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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scoped_guard(raw_spinlock_irqsave, &chv_lock)
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ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
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cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
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cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
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@ -1137,10 +1115,9 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
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static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
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unsigned long flags;
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u32 ctrl0;
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
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@ -1150,19 +1127,15 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
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chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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}
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static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
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u32 ctrl0, direction;
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unsigned long flags;
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raw_spin_lock_irqsave(&chv_lock, flags);
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ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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scoped_guard(raw_spinlock_irqsave, &chv_lock)
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ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
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direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
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direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
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@ -1203,23 +1176,20 @@ static void chv_gpio_irq_ack(struct irq_data *d)
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 intr_line;
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raw_spin_lock(&chv_lock);
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guard(raw_spinlock)(&chv_lock);
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intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
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intr_line &= CHV_PADCTRL0_INTSEL_MASK;
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intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
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chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
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raw_spin_unlock(&chv_lock);
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}
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static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
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{
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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u32 value, intr_line;
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unsigned long flags;
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
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intr_line &= CHV_PADCTRL0_INTSEL_MASK;
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@ -1231,8 +1201,6 @@ static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq
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else
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value |= BIT(intr_line);
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chv_pctrl_writel(pctrl, CHV_INTMASK, value);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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}
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static void chv_gpio_irq_mask(struct irq_data *d)
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@ -1257,7 +1225,15 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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{
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/*
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* Check if the interrupt has been requested with 0 as triggering
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* type. In that case it is assumed that the current values
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* type. If not, bail out, ...
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*/
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if (irqd_get_trigger_type(d) != IRQ_TYPE_NONE) {
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chv_gpio_irq_unmask(d);
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return 0;
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}
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/*
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* ...otherwise it is assumed that the current values
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* programmed to the hardware are used (e.g BIOS configured
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* defaults).
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*
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@ -1265,17 +1241,15 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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* read back the values from hardware now, set correct flow handler
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* and update mappings before the interrupt is being used.
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*/
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if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
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scoped_guard(raw_spinlock_irqsave, &chv_lock) {
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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struct device *dev = pctrl->dev;
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struct intel_community_context *cctx = &pctrl->context.communities[0];
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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irq_flow_handler_t handler;
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unsigned long flags;
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u32 intsel, value;
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raw_spin_lock_irqsave(&chv_lock, flags);
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intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
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intsel &= CHV_PADCTRL0_INTSEL_MASK;
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intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
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@ -1292,7 +1266,6 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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intsel, hwirq);
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cctx->intr_lines[intsel] = hwirq;
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}
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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}
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chv_gpio_irq_unmask(d);
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@ -1357,17 +1330,14 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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u32 value;
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int ret;
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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ret = chv_gpio_set_intr_line(pctrl, hwirq);
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if (ret) {
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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if (ret)
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return ret;
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}
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/*
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* Pins which can be used as shared interrupt are configured in
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@ -1408,8 +1378,6 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
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else if (type & IRQ_TYPE_LEVEL_MASK)
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irq_set_handler_locked(d, handle_level_irq);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return 0;
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}
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@ -1433,14 +1401,12 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
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struct intel_community_context *cctx = &pctrl->context.communities[0];
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long pending;
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unsigned long flags;
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u32 intr_line;
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chained_irq_enter(chip, desc);
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raw_spin_lock_irqsave(&chv_lock, flags);
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pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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scoped_guard(raw_spinlock_irqsave, &chv_lock)
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pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
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for_each_set_bit(intr_line, &pending, community->nirqs) {
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unsigned int offset;
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@ -1629,21 +1595,17 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
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void *handler_context, void *region_context)
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{
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struct intel_pinctrl *pctrl = region_context;
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unsigned long flags;
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acpi_status ret = AE_OK;
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raw_spin_lock_irqsave(&chv_lock, flags);
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guard(raw_spinlock_irqsave)(&chv_lock);
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if (function == ACPI_WRITE)
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chv_pctrl_writel(pctrl, address, *value);
|
||||
else if (function == ACPI_READ)
|
||||
*value = chv_pctrl_readl(pctrl, address);
|
||||
else
|
||||
ret = AE_BAD_PARAMETER;
|
||||
return AE_BAD_PARAMETER;
|
||||
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
|
||||
return ret;
|
||||
return AE_OK;
|
||||
}
|
||||
|
||||
static int chv_pinctrl_probe(struct platform_device *pdev)
|
||||
|
|
@ -1747,10 +1709,9 @@ static int chv_pinctrl_suspend_noirq(struct device *dev)
|
|||
{
|
||||
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
raw_spin_lock_irqsave(&chv_lock, flags);
|
||||
guard(raw_spinlock_irqsave)(&chv_lock);
|
||||
|
||||
cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
|
||||
|
||||
|
|
@ -1768,8 +1729,6 @@ static int chv_pinctrl_suspend_noirq(struct device *dev)
|
|||
ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1777,10 +1736,9 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
|
|||
{
|
||||
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
raw_spin_lock_irqsave(&chv_lock, flags);
|
||||
guard(raw_spinlock_irqsave)(&chv_lock);
|
||||
|
||||
/*
|
||||
* Mask all interrupts before restoring per-pin configuration
|
||||
|
|
@ -1822,8 +1780,6 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
|
|||
chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
|
||||
chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
|
||||
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue