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iommu/exynos: Use smarter TLB flush method for v5 SYSMMU
SYSMMU v5 has dedicated registers to perform TLB flush range operation, so use them instead of looping with FLUSH_ENTRY command. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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1 changed files with 16 additions and 4 deletions
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@ -171,6 +171,9 @@ static u32 lv2ent_offset(sysmmu_iova_t iova)
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#define REG_V5_PT_BASE_PFN 0x00C
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#define REG_V5_MMU_FLUSH_ALL 0x010
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#define REG_V5_MMU_FLUSH_ENTRY 0x014
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#define REG_V5_MMU_FLUSH_RANGE 0x018
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#define REG_V5_MMU_FLUSH_START 0x020
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#define REG_V5_MMU_FLUSH_END 0x024
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#define REG_V5_INT_STATUS 0x060
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#define REG_V5_INT_CLEAR 0x064
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#define REG_V5_FAULT_AR_VA 0x070
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@ -319,14 +322,23 @@ static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
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{
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unsigned int i;
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for (i = 0; i < num_inv; i++) {
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if (MMU_MAJ_VER(data->version) < 5)
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if (MMU_MAJ_VER(data->version) < 5) {
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for (i = 0; i < num_inv; i++) {
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writel((iova & SPAGE_MASK) | 1,
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data->sfrbase + REG_MMU_FLUSH_ENTRY);
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else
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iova += SPAGE_SIZE;
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}
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} else {
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if (num_inv == 1) {
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writel((iova & SPAGE_MASK) | 1,
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data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
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iova += SPAGE_SIZE;
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} else {
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writel((iova & SPAGE_MASK),
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data->sfrbase + REG_V5_MMU_FLUSH_START);
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writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE,
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data->sfrbase + REG_V5_MMU_FLUSH_END);
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writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE);
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}
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}
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}
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