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[ARM] S3C2412: Correct parents for EREFCLK and UREFCLK
For s3c2412, set parent for clk_erefclk and clk_urefclk. This allow for example to use xtal or extclk for i2s clock. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Matthieu Castet <matthieu.castet@parrot.com>
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9c3871ca59
commit
d5c52922b6
2 changed files with 13 additions and 2 deletions
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@ -631,6 +631,17 @@ static struct clk_init clks_src[] __initdata = {
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.bit = S3C2412_CLKSRC_USBCLK_HCLK,
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.src_0 = &clk_usysclk,
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.src_1 = &clk_h,
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/* here we assume OM[4] select xtal */
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}, {
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.clk = &clk_erefclk,
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.bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
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.src_0 = &clk_xtal,
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.src_1 = &clk_ext,
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}, {
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.clk = &clk_urefclk,
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.bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
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.src_0 = &clk_xtal,
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.src_1 = &clk_ext,
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},
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};
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@ -666,8 +677,6 @@ static void __init s3c2412_clk_initparents(void)
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static struct clk *clks[] __initdata = {
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&clk_ext,
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&clk_usb_bus,
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&clk_erefclk,
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&clk_urefclk,
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&clk_mrefclk,
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&clk_armclk,
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};
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@ -189,6 +189,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
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#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
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#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
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#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
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#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
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#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
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#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
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