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drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
02c4704bd2
commit
d5c87390f1
2 changed files with 41 additions and 32 deletions
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@ -175,6 +175,26 @@ static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
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}
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static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
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{
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
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0XFFFFFFFF);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
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}
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int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
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{
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u32 tmp;
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@ -199,22 +219,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
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gfxhub_v1_0_init_cache_regs(adev);
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gfxhub_v1_0_enable_system_domain(adev);
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/* Disable identity aperture.*/
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
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gfxhub_v1_0_disable_identity_aperture(adev);
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for (i = 0; i <= 14; i++) {
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
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@ -186,6 +186,25 @@ static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
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WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);
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}
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static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
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{
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
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0XFFFFFFFF);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
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}
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int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
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{
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u32 tmp;
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@ -210,22 +229,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
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mmhub_v1_0_init_cache_regs(adev);
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mmhub_v1_0_enable_system_domain(adev);
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/* Disable identity aperture.*/
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
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mmhub_v1_0_disable_identity_aperture(adev);
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for (i = 0; i <= 14; i++) {
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tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL)
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