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arm64: futex: Bound number of LDXR/STXR loops in FUTEX_WAKE_OP
commit03110a5cb2
upstream. Our futex implementation makes use of LDXR/STXR loops to perform atomic updates to user memory from atomic context. This can lead to latency problems if we end up spinning around the LL/SC sequence at the expense of doing something useful. Rework our futex atomic operations so that we return -EAGAIN if we fail to update the futex word after 128 attempts. The core futex code will reschedule if necessary and we'll try again later. Cc: <stable@kernel.org> Fixes:6170a97460
("arm64: Atomic operations") Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 34 additions and 21 deletions
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@ -23,26 +23,34 @@
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#include <asm/errno.h>
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#define FUTEX_MAX_LOOPS 128 /* What's the largest number you can think of? */
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#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \
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do { \
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unsigned int loops = FUTEX_MAX_LOOPS; \
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\
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uaccess_enable(); \
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asm volatile( \
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" prfm pstl1strm, %2\n" \
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"1: ldxr %w1, %2\n" \
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insn "\n" \
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"2: stlxr %w0, %w3, %2\n" \
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" cbnz %w0, 1b\n" \
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" dmb ish\n" \
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" cbz %w0, 3f\n" \
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" sub %w4, %w4, %w0\n" \
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" cbnz %w4, 1b\n" \
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" mov %w0, %w7\n" \
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"3:\n" \
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" dmb ish\n" \
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" .pushsection .fixup,\"ax\"\n" \
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" .align 2\n" \
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"4: mov %w0, %w5\n" \
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"4: mov %w0, %w6\n" \
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" b 3b\n" \
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" .popsection\n" \
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_ASM_EXTABLE(1b, 4b) \
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_ASM_EXTABLE(2b, 4b) \
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: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \
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: "r" (oparg), "Ir" (-EFAULT) \
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: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp), \
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"+r" (loops) \
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: "r" (oparg), "Ir" (-EFAULT), "Ir" (-EAGAIN) \
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: "memory"); \
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uaccess_disable(); \
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} while (0)
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@ -57,23 +65,23 @@ arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uaddr)
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mov %w3, %w4",
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__futex_atomic_op("mov %w3, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add %w3, %w1, %w4",
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__futex_atomic_op("add %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("orr %w3, %w1, %w4",
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__futex_atomic_op("orr %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and %w3, %w1, %w4",
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__futex_atomic_op("and %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("eor %w3, %w1, %w4",
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__futex_atomic_op("eor %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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default:
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@ -93,6 +101,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr,
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u32 oldval, u32 newval)
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{
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int ret = 0;
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unsigned int loops = FUTEX_MAX_LOOPS;
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u32 val, tmp;
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u32 __user *uaddr;
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@ -104,20 +113,24 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr,
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asm volatile("// futex_atomic_cmpxchg_inatomic\n"
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" prfm pstl1strm, %2\n"
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"1: ldxr %w1, %2\n"
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" sub %w3, %w1, %w4\n"
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" cbnz %w3, 3f\n"
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"2: stlxr %w3, %w5, %2\n"
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" cbnz %w3, 1b\n"
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" dmb ish\n"
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" sub %w3, %w1, %w5\n"
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" cbnz %w3, 4f\n"
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"2: stlxr %w3, %w6, %2\n"
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" cbz %w3, 3f\n"
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" sub %w4, %w4, %w3\n"
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" cbnz %w4, 1b\n"
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" mov %w0, %w8\n"
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"3:\n"
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" dmb ish\n"
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"4:\n"
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" .pushsection .fixup,\"ax\"\n"
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"4: mov %w0, %w6\n"
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" b 3b\n"
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"5: mov %w0, %w7\n"
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" b 4b\n"
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" .popsection\n"
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_ASM_EXTABLE(1b, 4b)
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_ASM_EXTABLE(2b, 4b)
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: "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
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: "r" (oldval), "r" (newval), "Ir" (-EFAULT)
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_ASM_EXTABLE(1b, 5b)
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_ASM_EXTABLE(2b, 5b)
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: "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp), "+r" (loops)
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: "r" (oldval), "r" (newval), "Ir" (-EFAULT), "Ir" (-EAGAIN)
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: "memory");
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uaccess_disable();
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