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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
sh: rework intc2 code
The shared intc2 code currently contains cpu-specific #ifdefs. This is a tad unclean and it prevents us from using the shared code to drive board-specific irqs on the se7780 board. This patch reworks the intc2 code by moving the base addresses of the intc2 registers into struct intc2_desc. This new structure also contains the name of the controller in struct irq_chip. The idea behind putting struct irq_chip in there is that we can use offsetof() to locate the base addresses in the irq_chip callbacks. One logic change has been made - the original shared intc2 code enabled the interrupts by default but with this patch they are all disabled by default. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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parent
d3efbdd6c5
commit
d619500aed
7 changed files with 103 additions and 75 deletions
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@ -16,28 +16,6 @@
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#include <asm/io.h>
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#include <asm/se7780.h>
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#define INTC_INTMSK0 0xFFD00044
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#define INTC_INTMSKCLR0 0xFFD00064
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static void disable_se7780_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift, INTC_INTMSK0 + p->msk_offset);
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}
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static void enable_se7780_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift, INTC_INTMSKCLR0 + p->msk_offset);
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}
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static struct irq_chip se7780_irq_chip __read_mostly = {
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.name = "SE7780",
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.mask = disable_se7780_irq,
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.unmask = enable_se7780_irq,
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.mask_ack = disable_se7780_irq,
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};
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static struct intc2_data intc2_irq_table[] = {
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{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT1 */
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{ 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT2 */
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@ -51,13 +29,24 @@ static struct intc2_data intc2_irq_table[] = {
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{ 0 , 0, 24, 0, 24, 3 }, /* SM501 */
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};
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static struct intc2_desc intc2_irq_desc __read_mostly = {
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.prio_base = 0, /* N/A */
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.msk_base = 0xffd00044,
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.mskclr_base = 0xffd00064,
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.intc2_data = intc2_irq_table,
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.nr_irqs = ARRAY_SIZE(intc2_irq_table),
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.chip = {
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.name = "INTC2-se7780",
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},
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};
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/*
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* Initialize IRQ setting
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*/
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void __init init_se7780_IRQ(void)
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{
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int i ;
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/* enable all interrupt at FPGA */
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ctrl_outw(0, FPGA_INTMSK1);
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/* mask SM501 interrupt */
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@ -79,11 +68,5 @@ void __init init_se7780_IRQ(void)
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/* FPGA + 0x0A */
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ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
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for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++) {
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disable_irq_nosync(intc2_irq_table[i].irq);
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set_irq_chip_and_handler_name( intc2_irq_table[i].irq, &se7780_irq_chip,
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handle_level_irq, "level");
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set_irq_chip_data( intc2_irq_table[i].irq, &intc2_irq_table[i] );
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disable_se7780_irq(intc2_irq_table[i].irq);
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}
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register_intc2_controller(&intc2_irq_desc);
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}
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@ -14,36 +14,26 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7760)
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#define INTC2_BASE 0xfe080000
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#define INTC2_INTMSK (INTC2_BASE + 0x40)
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#define INTC2_INTMSKCLR (INTC2_BASE + 0x60)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785)
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#define INTC2_BASE 0xffd40000
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#define INTC2_INTMSK (INTC2_BASE + 0x38)
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#define INTC2_INTMSKCLR (INTC2_BASE + 0x3c)
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#endif
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static inline struct intc2_desc *get_intc2_desc(unsigned int irq)
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{
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struct irq_chip *chip = get_irq_chip(irq);
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return (void *)((char *)chip - offsetof(struct intc2_desc, chip));
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}
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static void disable_intc2_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift, INTC2_INTMSK + p->msk_offset);
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struct intc2_desc *d = get_intc2_desc(irq);
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ctrl_outl(1 << p->msk_shift, d->msk_base + p->msk_offset);
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}
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static void enable_intc2_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift, INTC2_INTMSKCLR + p->msk_offset);
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struct intc2_desc *d = get_intc2_desc(irq);
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ctrl_outl(1 << p->msk_shift, d->mskclr_base + p->msk_offset);
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}
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static struct irq_chip intc2_irq_chip = {
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.name = "INTC2",
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.mask = disable_intc2_irq,
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.unmask = enable_intc2_irq,
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.mask_ack = disable_intc2_irq,
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};
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/*
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* Setup an INTC2 style interrupt.
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* NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
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@ -56,30 +46,36 @@ static struct irq_chip intc2_irq_chip = {
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*
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* in the intc2_data table.
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*/
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void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs)
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void register_intc2_controller(struct intc2_desc *desc)
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{
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int i;
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for (i = 0; i < nr_irqs; i++) {
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desc->chip.mask = disable_intc2_irq;
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desc->chip.unmask = enable_intc2_irq;
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desc->chip.mask_ack = disable_intc2_irq;
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for (i = 0; i < desc->nr_irqs; i++) {
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unsigned long ipr, flags;
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struct intc2_data *p = table + i;
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struct intc2_data *p = desc->intc2_data + i;
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disable_irq_nosync(p->irq);
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/* Set the priority level */
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local_irq_save(flags);
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if (desc->prio_base) {
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/* Set the priority level */
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local_irq_save(flags);
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ipr = ctrl_inl(INTC2_BASE + p->ipr_offset);
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ipr &= ~(0xf << p->ipr_shift);
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ipr |= p->priority << p->ipr_shift;
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ctrl_outl(ipr, INTC2_BASE + p->ipr_offset);
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ipr = ctrl_inl(desc->prio_base + p->ipr_offset);
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ipr &= ~(0xf << p->ipr_shift);
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ipr |= p->priority << p->ipr_shift;
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ctrl_outl(ipr, desc->prio_base + p->ipr_offset);
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local_irq_restore(flags);
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local_irq_restore(flags);
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}
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set_irq_chip_and_handler_name(p->irq, &intc2_irq_chip,
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set_irq_chip_and_handler_name(p->irq, &desc->chip,
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handle_level_irq, "level");
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set_irq_chip_data(p->irq, p);
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enable_intc2_irq(p->irq);
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disable_intc2_irq(p->irq);
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}
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}
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@ -96,6 +96,19 @@ static struct intc2_data intc2_irq_table[] = {
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{109,12, 0, 4, 0, 3}, /* CMTI */
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};
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static struct intc2_desc intc2_irq_desc __read_mostly = {
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.prio_base = 0xfe080000,
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.msk_base = 0xfe080040,
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.mskclr_base = 0xfe080060,
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.intc2_data = intc2_irq_table,
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.nr_irqs = ARRAY_SIZE(intc2_irq_table),
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.chip = {
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.name = "INTC2-sh7760",
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},
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};
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static struct ipr_data sh7760_ipr_map[] = {
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/* IRQ, IPR-idx, shift, priority */
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{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
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@ -143,7 +156,7 @@ unsigned int map_ipridx_to_addr(int idx)
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void __init init_IRQ_intc2(void)
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{
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make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
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register_intc2_controller(&intc2_irq_desc);
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}
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void __init init_IRQ_ipr(void)
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@ -102,7 +102,20 @@ static struct intc2_data intc2_irq_table[] = {
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{ 68, 0x14, 8, 0, 18, 2 }, /* PCIC4 */
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};
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static struct intc2_desc intc2_irq_desc __read_mostly = {
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.prio_base = 0xffd40000,
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.msk_base = 0xffd40038,
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.mskclr_base = 0xffd4003c,
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.intc2_data = intc2_irq_table,
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.nr_irqs = ARRAY_SIZE(intc2_irq_table),
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.chip = {
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.name = "INTC2-sh7780",
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},
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};
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void __init init_IRQ_intc2(void)
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{
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make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
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register_intc2_controller(&intc2_irq_desc);
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}
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@ -97,7 +97,21 @@ static struct intc2_data intc2_irq_table[] = {
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{ 60, 12, 16, 0, 7, 3 }, /* SCIF5 ERI, RXI, BRI, TXI */
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};
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static struct intc2_desc intc2_irq_desc __read_mostly = {
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.prio_base = 0xffd40000,
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.msk_base = 0xffd40038,
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.mskclr_base = 0xffd4003c,
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.intc2_data = intc2_irq_table,
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.nr_irqs = ARRAY_SIZE(intc2_irq_table),
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.chip = {
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.name = "INTC2-sh7785",
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},
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};
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void __init init_IRQ_intc2(void)
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{
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make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
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register_intc2_controller(&intc2_irq_desc);
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}
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@ -5,4 +5,23 @@
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extern atomic_t irq_err_count;
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struct intc2_data {
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unsigned short irq;
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unsigned char ipr_offset, ipr_shift;
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unsigned char msk_offset, msk_shift;
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unsigned char priority;
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};
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struct intc2_desc {
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unsigned long prio_base;
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unsigned long msk_base;
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unsigned long mskclr_base;
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struct intc2_data *intc2_data;
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unsigned int nr_irqs;
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struct irq_chip chip;
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};
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void register_intc2_controller(struct intc2_desc *);
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void init_IRQ_intc2(void);
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#endif /* __ASM_SH_HW_IRQ_H */
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@ -63,16 +63,6 @@ void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
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void make_imask_irq(unsigned int irq);
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void init_IRQ_ipr(void);
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struct intc2_data {
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unsigned short irq;
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unsigned char ipr_offset, ipr_shift;
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unsigned char msk_offset, msk_shift;
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unsigned char priority;
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};
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void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
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void init_IRQ_intc2(void);
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static inline int generic_irq_demux(int irq)
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{
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return irq;
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