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media: TDA1997x: replace video detection routine
The TDA1997x (HDMI receiver) driver currently uses a specific video format detection scheme. The frame (or field in interlaced mode), line and HSync pulse durations are compared to those of known, standard video modes. If a match is found, the mode is assumed to be detected, otherwise -ERANGE is returned (then possibly ignored). This means that: - another mode with similar timings will be detected incorrectly (e.g. 2x faster clock and lines twice as long) - non-standard modes will not work. This patch replaces this scheme with a direct read of geometry registers. This way all modes recognized by the chip are supported. In interlaced modes, the code assumes the V sync signal has the same duration for both fields. While this may be not necessarily true, I can't see any way to get the "other" V sync width. This is most probably harmless. All tests have been performed on Gateworks' Ventana GW54xx board, with a TDA19971 chip. Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl> Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Krzysztof Hałasa
Mauro Carvalho Chehab
parent
3ae5c3bc07
commit
d64a7709a8
2 changed files with 68 additions and 50 deletions
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@ -1092,67 +1092,82 @@ tda1997x_detect_std(struct tda1997x_state *state,
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struct v4l2_dv_timings *timings)
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{
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struct v4l2_subdev *sd = &state->sd;
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u32 vper;
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u16 hper;
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u16 hsper;
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int i;
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/*
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* Read the FMT registers
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* REG_V_PER: Period of a frame (or two fields) in MCLK(27MHz) cycles
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* REG_H_PER: Period of a line in MCLK(27MHz) cycles
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* REG_HS_WIDTH: Period of horiz sync pulse in MCLK(27MHz) cycles
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* REG_V_PER: Period of a frame (or field) in MCLK (27MHz) cycles
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* REG_H_PER: Period of a line in MCLK (27MHz) cycles
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* REG_HS_WIDTH: Period of horiz sync pulse in MCLK (27MHz) cycles
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*/
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vper = io_read24(sd, REG_V_PER) & MASK_VPER;
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hper = io_read16(sd, REG_H_PER) & MASK_HPER;
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hsper = io_read16(sd, REG_HS_WIDTH) & MASK_HSWIDTH;
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v4l2_dbg(1, debug, sd, "Signal Timings: %u/%u/%u\n", vper, hper, hsper);
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u32 vper, vsync_pos;
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u16 hper, hsync_pos, hsper, interlaced;
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u16 htot, hact, hfront, hsync, hback;
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u16 vtot, vact, vfront1, vfront2, vsync, vback1, vback2;
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if (!state->input_detect[0] && !state->input_detect[1])
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return -ENOLINK;
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for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
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const struct v4l2_bt_timings *bt;
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u32 lines, width, _hper, _hsper;
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u32 vmin, vmax, hmin, hmax, hsmin, hsmax;
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bool vmatch, hmatch, hsmatch;
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vper = io_read24(sd, REG_V_PER);
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hper = io_read16(sd, REG_H_PER);
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hsper = io_read16(sd, REG_HS_WIDTH);
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vsync_pos = vper & MASK_VPER_SYNC_POS;
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hsync_pos = hper & MASK_HPER_SYNC_POS;
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interlaced = hsper & MASK_HSWIDTH_INTERLACED;
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vper &= MASK_VPER;
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hper &= MASK_HPER;
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hsper &= MASK_HSWIDTH;
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v4l2_dbg(1, debug, sd, "Signal Timings: %u/%u/%u\n", vper, hper, hsper);
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bt = &v4l2_dv_timings_presets[i].bt;
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width = V4L2_DV_BT_FRAME_WIDTH(bt);
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lines = V4L2_DV_BT_FRAME_HEIGHT(bt);
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_hper = (u32)bt->pixelclock / width;
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if (bt->interlaced)
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lines /= 2;
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/* vper +/- 0.7% */
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vmin = ((27000000 / 1000) * 993) / _hper * lines;
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vmax = ((27000000 / 1000) * 1007) / _hper * lines;
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/* hper +/- 1.0% */
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hmin = ((27000000 / 100) * 99) / _hper;
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hmax = ((27000000 / 100) * 101) / _hper;
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/* hsper +/- 2 (take care to avoid 32bit overflow) */
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_hsper = 27000 * bt->hsync / ((u32)bt->pixelclock/1000);
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hsmin = _hsper - 2;
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hsmax = _hsper + 2;
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htot = io_read16(sd, REG_FMT_H_TOT);
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hact = io_read16(sd, REG_FMT_H_ACT);
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hfront = io_read16(sd, REG_FMT_H_FRONT);
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hsync = io_read16(sd, REG_FMT_H_SYNC);
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hback = io_read16(sd, REG_FMT_H_BACK);
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/* vmatch matches the framerate */
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vmatch = ((vper <= vmax) && (vper >= vmin)) ? 1 : 0;
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/* hmatch matches the width */
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hmatch = ((hper <= hmax) && (hper >= hmin)) ? 1 : 0;
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/* hsmatch matches the hswidth */
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hsmatch = ((hsper <= hsmax) && (hsper >= hsmin)) ? 1 : 0;
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if (hmatch && vmatch && hsmatch) {
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v4l2_print_dv_timings(sd->name, "Detected format: ",
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&v4l2_dv_timings_presets[i],
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false);
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if (timings)
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*timings = v4l2_dv_timings_presets[i];
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return 0;
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}
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vtot = io_read16(sd, REG_FMT_V_TOT);
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vact = io_read16(sd, REG_FMT_V_ACT);
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vfront1 = io_read(sd, REG_FMT_V_FRONT_F1);
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vfront2 = io_read(sd, REG_FMT_V_FRONT_F2);
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vsync = io_read(sd, REG_FMT_V_SYNC);
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vback1 = io_read(sd, REG_FMT_V_BACK_F1);
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vback2 = io_read(sd, REG_FMT_V_BACK_F2);
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v4l2_dbg(1, debug, sd, "Geometry: H %u %u %u %u %u Sync%c V %u %u %u %u %u %u %u Sync%c\n",
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htot, hact, hfront, hsync, hback, hsync_pos ? '+' : '-',
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vtot, vact, vfront1, vfront2, vsync, vback1, vback2, vsync_pos ? '+' : '-');
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if (!timings)
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return 0;
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timings->type = V4L2_DV_BT_656_1120;
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timings->bt.width = hact;
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timings->bt.hfrontporch = hfront;
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timings->bt.hsync = hsync;
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timings->bt.hbackporch = hback;
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timings->bt.height = vact;
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timings->bt.vfrontporch = vfront1;
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timings->bt.vsync = vsync;
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timings->bt.vbackporch = vback1;
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timings->bt.interlaced = interlaced ? V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
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timings->bt.polarities = vsync_pos ? V4L2_DV_VSYNC_POS_POL : 0;
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timings->bt.polarities |= hsync_pos ? V4L2_DV_HSYNC_POS_POL : 0;
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timings->bt.pixelclock = (u64)htot * vtot * 27000000;
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if (interlaced) {
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timings->bt.il_vfrontporch = vfront2;
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timings->bt.il_vsync = timings->bt.vsync;
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timings->bt.il_vbackporch = vback2;
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do_div(timings->bt.pixelclock, vper * 2 /* full frame */);
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} else {
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timings->bt.il_vfrontporch = 0;
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timings->bt.il_vsync = 0;
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timings->bt.il_vbackporch = 0;
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do_div(timings->bt.pixelclock, vper);
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}
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v4l_err(state->client, "no resolution match for timings: %d/%d/%d\n",
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vper, hper, hsper);
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return -ERANGE;
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v4l2_find_dv_timings_cap(timings, &tda1997x_dv_timings_cap,
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(u32)timings->bt.pixelclock / 500, NULL, NULL);
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v4l2_print_dv_timings(sd->name, "Detected format: ", timings, false);
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return 0;
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}
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/* some sort of errata workaround for chip revision 0 (N1) */
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@ -117,9 +117,12 @@
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#define REG_CURPAGE_00H 0xFF
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#define MASK_VPER 0x3fffff
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#define MASK_VPER_SYNC_POS 0x800000
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#define MASK_VHREF 0x3fff
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#define MASK_HPER 0x0fff
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#define MASK_HPER_SYNC_POS 0x8000
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#define MASK_HSWIDTH 0x03ff
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#define MASK_HSWIDTH_INTERLACED 0x8000
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/* HPD Detection */
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#define DETECT_UTIL BIT(7) /* utility of HDMI level */
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