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gma500: Program the DPLL lane based on the selected digitial port
Based on the spec, the CRT output doesn't use the lane. And the HDMI B output uses the Lane0/1 while the HDMI C output uses the Lane 2/3. But currently it will program all the four lanes for the CRT/HDMI. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> [Ported to the in-kernel driver] Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
25e9dc6970
commit
d66760962d
3 changed files with 56 additions and 29 deletions
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@ -57,8 +57,14 @@ struct cdv_intel_clock_t {
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struct cdv_intel_limit_t {
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struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1;
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struct cdv_intel_p2_t p2;
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bool (*find_pll)(const struct cdv_intel_limit_t *, struct drm_crtc *,
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int, int, struct cdv_intel_clock_t *);
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};
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static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit,
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struct drm_crtc *crtc, int target, int refclk,
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struct cdv_intel_clock_t *best_clock);
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#define CDV_LIMIT_SINGLE_LVDS_96 0
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#define CDV_LIMIT_SINGLE_LVDS_100 1
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#define CDV_LIMIT_DAC_HDMI_27 2
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@ -76,6 +82,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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.p1 = {.min = 2, .max = 10},
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.p2 = {.dot_limit = 200000,
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.p2_slow = 14, .p2_fast = 14},
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.find_pll = cdv_intel_find_best_PLL,
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},
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{ /* CDV_SINGLE_LVDS_100MHz */
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.dot = {.min = 20000, .max = 115500},
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@ -90,6 +97,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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* is 80-224Mhz. Prefer single channel as much as possible.
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*/
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.p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
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.find_pll = cdv_intel_find_best_PLL,
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},
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{ /* CDV_DAC_HDMI_27MHz */
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.dot = {.min = 20000, .max = 400000},
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@ -101,6 +109,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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.p = {.min = 5, .max = 90},
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.p1 = {.min = 1, .max = 9},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
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.find_pll = cdv_intel_find_best_PLL,
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},
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{ /* CDV_DAC_HDMI_96MHz */
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.dot = {.min = 20000, .max = 400000},
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@ -112,6 +121,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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.p = {.min = 5, .max = 100},
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.p1 = {.min = 1, .max = 10},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
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.find_pll = cdv_intel_find_best_PLL,
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},
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};
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@ -216,7 +226,7 @@ static void cdv_sb_reset(struct drm_device *dev)
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*/
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static int
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cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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struct cdv_intel_clock_t *clock, bool is_lvds)
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struct cdv_intel_clock_t *clock, bool is_lvds, u32 ddi_select)
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{
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struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
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int pipe = psb_crtc->pipe;
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@ -336,30 +346,33 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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if (ret)
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return ret;
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lane_reg = PSB_LANE0;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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if (ddi_select) {
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if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
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lane_reg = PSB_LANE0;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE1;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE2;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE3;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE1;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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} else {
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lane_reg = PSB_LANE2;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE3;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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}
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}
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return 0;
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}
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@ -438,13 +451,12 @@ static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc,
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return true;
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}
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static bool cdv_intel_find_best_PLL(struct drm_crtc *crtc, int target,
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int refclk,
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struct cdv_intel_clock_t *best_clock)
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static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit,
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struct drm_crtc *crtc, int target, int refclk,
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struct cdv_intel_clock_t *best_clock)
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{
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struct drm_device *dev = crtc->dev;
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struct cdv_intel_clock_t clock;
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const struct cdv_intel_limit_t *limit = cdv_intel_limit(crtc, refclk);
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int err = target;
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@ -954,6 +966,8 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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bool is_hdmi = false;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *connector;
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const struct cdv_intel_limit_t *limit;
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u32 ddi_select = 0;
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list_for_each_entry(connector, &mode_config->connector_list, head) {
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struct psb_intel_encoder *psb_intel_encoder =
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@ -963,6 +977,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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|| connector->encoder->crtc != crtc)
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continue;
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ddi_select = psb_intel_encoder->ddi_select;
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switch (psb_intel_encoder->type) {
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case INTEL_OUTPUT_LVDS:
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is_lvds = true;
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@ -976,6 +991,9 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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case INTEL_OUTPUT_HDMI:
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is_hdmi = true;
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break;
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default:
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DRM_ERROR("invalid output type.\n");
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return 0;
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}
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}
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@ -992,8 +1010,10 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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drm_mode_debug_printmodeline(adjusted_mode);
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limit = cdv_intel_limit(crtc, refclk);
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ok = cdv_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
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ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
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&clock);
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if (!ok) {
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dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
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@ -1032,7 +1052,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
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REG_READ(map->dpll);
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cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds);
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cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
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udelay(150);
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@ -352,9 +352,11 @@ void cdv_hdmi_init(struct drm_device *dev,
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switch (reg) {
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case SDVOB:
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ddc_bus = GPIOE;
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psb_intel_encoder->ddi_select = DDI0_SELECT;
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break;
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case SDVOC:
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ddc_bus = GPIOD;
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psb_intel_encoder->ddi_select = DDI1_SELECT;
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break;
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default:
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DRM_ERROR("unknown reg 0x%x for HDMI\n", reg);
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@ -133,6 +133,11 @@ struct psb_intel_encoder {
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void (*hot_plug)(struct psb_intel_encoder *);
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int crtc_mask;
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int clone_mask;
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u32 ddi_select; /* Channel info */
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#define DDI0_SELECT 0x01
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#define DDI1_SELECT 0x02
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#define DP_MASK 0x8000;
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#define DDI_MASK 0x03
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void *dev_priv; /* For sdvo_priv, lvds_priv, etc... */
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/* FIXME: Either make SDVO and LVDS store it's i2c here or give CDV it's
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