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drm/amd/powerplay: add power profile support for Vega10 (v2)
This implements the workload specific interface of optimized compute power profile for Vega10. v2: squash in fix (Tom) Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 92 additions and 0 deletions
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@ -2286,6 +2286,34 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
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return 0;
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}
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static int vega10_save_default_power_profile(struct pp_hwmgr *hwmgr)
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{
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struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
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struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
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uint32_t min_level;
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hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
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hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
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/* Optimize compute power profile: Use only highest
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* 2 power levels (if more than 2 are available)
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*/
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if (dpm_table->count > 2)
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min_level = dpm_table->count - 2;
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else if (dpm_table->count == 2)
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min_level = 1;
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else
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min_level = 0;
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hwmgr->default_compute_power_profile.min_sclk =
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dpm_table->dpm_levels[min_level].value;
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hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
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hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
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return 0;
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}
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/**
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* Initializes the SMC table and uploads it
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*
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@ -2420,6 +2448,8 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
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PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
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return result);
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vega10_save_default_power_profile(hwmgr);
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return 0;
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}
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@ -4483,6 +4513,67 @@ static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
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return result;
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}
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static void vega10_find_min_clock_index(struct pp_hwmgr *hwmgr,
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uint32_t *sclk_idx, uint32_t *mclk_idx,
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uint32_t min_sclk, uint32_t min_mclk)
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{
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struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
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struct vega10_dpm_table *dpm_table = &(data->dpm_table);
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uint32_t i;
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for (i = 0; i < dpm_table->gfx_table.count; i++) {
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if (dpm_table->gfx_table.dpm_levels[i].enabled &&
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dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
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*sclk_idx = i;
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break;
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}
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}
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for (i = 0; i < dpm_table->mem_table.count; i++) {
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if (dpm_table->mem_table.dpm_levels[i].enabled &&
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dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
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*mclk_idx = i;
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break;
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}
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}
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}
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static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
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struct amd_pp_profile *request)
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{
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struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
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uint32_t sclk_idx = 0, mclk_idx = 0;
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
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return -EINVAL;
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vega10_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx,
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request->min_sclk, request->min_mclk);
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if (sclk_idx) {
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if (!data->registry_data.sclk_dpm_key_disabled)
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PP_ASSERT_WITH_CODE(
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!smum_send_msg_to_smc_with_parameter(
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hwmgr->smumgr,
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PPSMC_MSG_SetSoftMinGfxclkByIndex,
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sclk_idx),
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"Failed to set soft min sclk index!",
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return -EINVAL);
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}
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if (mclk_idx) {
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if (!data->registry_data.mclk_dpm_key_disabled)
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PP_ASSERT_WITH_CODE(
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!smum_send_msg_to_smc_with_parameter(
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hwmgr->smumgr,
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PPSMC_MSG_SetSoftMinUclkByIndex,
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mclk_idx),
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"Failed to set soft min mclk index!",
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return -EINVAL);
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}
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return 0;
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}
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static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
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.backend_init = vega10_hwmgr_backend_init,
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@ -4531,6 +4622,7 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
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vega10_check_smc_update_required_for_display_configuration,
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.power_off_asic = vega10_power_off_asic,
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.disable_smc_firmware_ctf = vega10_thermal_disable_alert,
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.set_power_profile_state = vega10_set_power_profile_state,
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};
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int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
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