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irqchip/gic: Isolate early GIC initialisation code
To re-use the code that initialises the GIC (found in __gic_init_bases()), from within a platform driver, it is necessary to move the code from the __init section so that it is always present and not removed. Unfortunately, it is not possible to simply drop the __init from the function declaration for __gic_init_bases() because it contains calls to set_smp_cross_call() and set_handle_irq() which are both located in the __init section. Fortunately, these calls are only required for the root controller and because the initial platform driver will only support non-root controllers that can be initialised later in the boot process, we can move these calls to another function. Move the bulk of the code from __gic_init_bases() to a new function called gic_init_bases() which is not located in the __init section and can be used by the platform driver. Update __gic_init_bases() to call gic_init_bases() and if necessary, set_smp_cross_call() and set_handle_irq(). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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be45beb2df
commit
d6ce564cea
1 changed files with 32 additions and 23 deletions
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@ -1032,14 +1032,11 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
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.unmap = gic_irq_domain_unmap,
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.unmap = gic_irq_domain_unmap,
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};
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};
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static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start,
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static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
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struct fwnode_handle *handle)
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struct fwnode_handle *handle)
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{
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{
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irq_hw_number_t hwirq_base;
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irq_hw_number_t hwirq_base;
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int gic_irqs, irq_base, i, ret;
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int gic_irqs, irq_base, ret;
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if (WARN_ON(!gic || gic->domain))
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return -EINVAL;
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/* Initialize irq_chip */
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/* Initialize irq_chip */
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gic->chip = gic_chip;
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gic->chip = gic_chip;
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@ -1138,23 +1135,6 @@ static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start,
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goto error;
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goto error;
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}
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}
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if (gic == &gic_data[0]) {
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/*
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* Initialize the CPU interface map to all CPUs.
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* It will be refined as each CPU probes its ID.
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* This is only necessary for the primary GIC.
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*/
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for (i = 0; i < NR_GIC_CPU_IF; i++)
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gic_cpu_map[i] = 0xff;
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#ifdef CONFIG_SMP
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set_smp_cross_call(gic_raise_softirq);
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register_cpu_notifier(&gic_cpu_notifier);
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#endif
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set_handle_irq(gic_handle_irq);
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if (static_key_true(&supports_deactivate))
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pr_info("GIC: Using split EOI/Deactivate mode\n");
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}
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gic_dist_init(gic);
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gic_dist_init(gic);
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ret = gic_cpu_init(gic);
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ret = gic_cpu_init(gic);
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if (ret)
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if (ret)
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@ -1177,6 +1157,35 @@ static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start,
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return ret;
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return ret;
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}
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}
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static int __init __gic_init_bases(struct gic_chip_data *gic,
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int irq_start,
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struct fwnode_handle *handle)
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{
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int i;
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if (WARN_ON(!gic || gic->domain))
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return -EINVAL;
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if (gic == &gic_data[0]) {
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/*
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* Initialize the CPU interface map to all CPUs.
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* It will be refined as each CPU probes its ID.
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* This is only necessary for the primary GIC.
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*/
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for (i = 0; i < NR_GIC_CPU_IF; i++)
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gic_cpu_map[i] = 0xff;
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#ifdef CONFIG_SMP
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set_smp_cross_call(gic_raise_softirq);
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register_cpu_notifier(&gic_cpu_notifier);
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#endif
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set_handle_irq(gic_handle_irq);
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if (static_key_true(&supports_deactivate))
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pr_info("GIC: Using split EOI/Deactivate mode\n");
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}
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return gic_init_bases(gic, irq_start, handle);
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}
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void __init gic_init(unsigned int gic_nr, int irq_start,
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void __init gic_init(unsigned int gic_nr, int irq_start,
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void __iomem *dist_base, void __iomem *cpu_base)
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void __iomem *dist_base, void __iomem *cpu_base)
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{
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{
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