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[MIPS] Tinker with constraints in <asm/atomic.h> to fix build error.
[...] CC init/main.o include/asm/bitops.h: In function `start_kernel': include/asm/bitops.h:76: warning: asm operand 2 probably doesn't match constraints include/asm/bitops.h:76: warning: asm operand 2 probably doesn't match constraints include/asm/bitops.h:76: warning: asm operand 2 probably doesn't match constraints include/asm/bitops.h:76: error: impossible constraint in `asm' include/asm/bitops.h:76: error: impossible constraint in `asm' include/asm/bitops.h:76: error: impossible constraint in `asm' make[1]: *** [init/main.o] Error 1 [...] The build error is caused by the ages old gcc bug where gcc at the time of analyzing the constraints is unable to figure out that an "i" constraint actually can be satisfied and thus will abort unless an "r" is added to the constraint. For the actual code generation gcc will only ever use the "i" constraint. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 3 additions and 3 deletions
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@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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"2: b 1b \n"
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" .previous \n"
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: "=&r" (temp), "=m" (*m)
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: "i" (bit), "m" (*m), "r" (~0));
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: "ir" (bit), "m" (*m), "r" (~0));
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#endif /* CONFIG_CPU_MIPSR2 */
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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"2: b 1b \n"
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" .previous \n"
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: "=&r" (temp), "=m" (*m)
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: "i" (bit), "m" (*m));
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: "ir" (bit), "m" (*m));
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#endif /* CONFIG_CPU_MIPSR2 */
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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"2: b 1b \n"
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" .previous \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "i" (bit), "m" (*m)
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: "ir" (bit), "m" (*m)
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: "memory");
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#endif
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} else if (cpu_has_llsc) {
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