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ARM: imx6q: Set enet tx reference clk from anatop to support 1588
Set GRP1 BIT21 ENET_CLK_SEL: Enet tx reference clk from internal clock from anatop (loopback through pad), this clock also sent out to external PHY Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 12 additions and 0 deletions
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@ -117,6 +117,17 @@ static void __init imx6q_sabrelite_init(void)
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imx6q_sabrelite_cko1_setup();
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}
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static void __init imx6q_1588_init(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
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if (!IS_ERR(gpr))
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regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
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else
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pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
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}
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static void __init imx6q_usb_init(void)
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{
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struct regmap *anatop;
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@ -153,6 +164,7 @@ static void __init imx6q_init_machine(void)
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imx6q_pm_init();
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imx6q_usb_init();
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imx6q_1588_init();
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}
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static struct cpuidle_driver imx6q_cpuidle_driver = {
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