docs: watchdog: mlx-wdt: Add description of new watchdog type 3
Add documentation with details of new type of Mellanox watchdog driver. Signed-off-by: Michael Shych <michaelsh@mellanox.com> Reviewed-by: Vadim Pasternak <vadimp@mellanox.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20200504141427.17685-5-michaelsh@mellanox.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
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@ -24,10 +24,19 @@ Type 2:
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Maximum timeout is 255 sec.
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Maximum timeout is 255 sec.
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Get time-left is supported.
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Get time-left is supported.
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Type 3:
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Same as Type 2 with extended maximum timeout period.
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Maximum timeout is 65535 sec.
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Type 1 HW watchdog implementation exist in old systems and
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Type 1 HW watchdog implementation exist in old systems and
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all new systems have type 2 HW watchdog.
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all new systems have type 2 HW watchdog.
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Two types of HW implementation have also different register map.
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Two types of HW implementation have also different register map.
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Type 3 HW watchdog implementation can exist on all Mellanox systems
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with new programmer logic device.
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It's differentiated by WD capability bit.
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Old systems still have only one main watchdog.
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Mellanox system can have 2 watchdogs: main and auxiliary.
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Mellanox system can have 2 watchdogs: main and auxiliary.
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Main and auxiliary watchdog devices can be enabled together
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Main and auxiliary watchdog devices can be enabled together
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on the same system.
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on the same system.
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@ -54,3 +63,4 @@ The driver checks during initialization if the previous system reset
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was done by the watchdog. If yes, it makes a notification about this event.
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was done by the watchdog. If yes, it makes a notification about this event.
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Access to HW registers is performed through a generic regmap interface.
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Access to HW registers is performed through a generic regmap interface.
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Programmable logic device registers have little-endian order.
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