mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 13:55:32 +00:00
The imx fixes for 3.11:
* A few device tree source fixes regarding pinctrl, clock, and pwm backlight. * Fixes imx28 and imx51 audio driver failure caused by sgtl5000 codec driver change by supplying the correct clock for codec. * imx6q emi_sel clock muxing and imx6q-iomuxc-gpr macro fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJR5B55AAoJEFBXWFqHsHzOEGoH/2DesLDZkQbUCn+w7Z3H7HYi QAPeG1F/Ke3cBSaT+v/Z+46MgmU2gyQkxk08GRtPuVAZwCuWxSUN1H6+yakeBdHb XGXR25RbbASIpYdYnC37eKiU2itiBmD7CRbWJ5xPHEluAgr47vr3OKfls6laii3b nSM4sKz45PxBJ55M0qcE+A6oVdf9c+G0vm0aX14xEiLEUghB/U0KNKWp+B63hwfh tg11gNwr2dO8jv51xpwJXH17juoZ46srOzmxERJm3j08JSz/tJSvIQajSsg54aLT pAxToPAeuGGga5+7AanGT+repzZdd74Lp3U/lGw6WpaxLOpFf5Am3841O8qqCLw= =q0LM -----END PGP SIGNATURE----- Merge tag 'imx-fixes-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes From Shawn Guo, imx fixes for 3.11: - A few device tree source fixes regarding pinctrl, clock, and pwm backlight. - Fixes imx28 and imx51 audio driver failure caused by sgtl5000 codec driver change by supplying the correct clock for codec. - imx6q emi_sel clock muxing and imx6q-iomuxc-gpr macro fixes * tag 'imx-fixes-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: dts: imx51-babbage: Pass a real clock to the codec ARM i.MX53: mba53: Fix PWM backlight DT node ARM: imx: fix vf610 enet module clock selection ARM: mxs: saif0 is the clock provider to sgtl5000 ARM: i.MX6Q: correct emi_sel clock muxing ARM i.MX6Q: Fix IOMUXC GPR1 defines for ENET_CLK_SEL and IPU1/2_MUX ARM: i.MX27: Typo fix ARM: imx27: Fix documentation for SPLL clock ARM i.MX53: Fix UART pad configuration
This commit is contained in:
commit
d757380c11
14 changed files with 55 additions and 37 deletions
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@ -98,6 +98,7 @@ clocks and IDs.
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fpm 83
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mpll_osc_sel 84
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mpll_sel 85
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spll_gate 86
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Examples:
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@ -147,7 +147,7 @@ sgtl5000: codec@0a {
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reg = <0x0a>;
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VDDA-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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clocks = <&saif0>;
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};
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pcf8563: rtc@51 {
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@ -195,7 +195,7 @@ sgtl5000: codec@0a {
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reg = <0x0a>;
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VDDA-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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clocks = <&saif0>;
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};
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at24@51 {
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@ -184,7 +184,7 @@ sgtl5000: codec@0a {
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reg = <0x0a>;
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VDDA-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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clocks = <&saif0>;
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};
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eeprom: eeprom@51 {
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@ -837,6 +837,7 @@ saif0: saif@80042000 {
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compatible = "fsl,imx28-saif";
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reg = <0x80042000 0x2000>;
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interrupts = <59 80>;
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#clock-cells = <0>;
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clocks = <&clks 53>;
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dmas = <&dma_apbx 4>;
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dma-names = "rx-tx";
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@ -61,6 +61,16 @@ sound {
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mux-int-port = <2>;
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mux-ext-port = <3>;
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};
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clocks {
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clk_26M: codec_clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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gpios = <&gpio4 26 1>;
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};
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};
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};
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&esdhc1 {
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@ -229,6 +239,7 @@ MX51_PAD_GPIO1_6__GPIO1_6 0x100
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MX51_PAD_EIM_A27__GPIO2_21 0x5
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MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
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MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
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MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
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>;
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};
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};
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@ -255,7 +266,7 @@ &i2c2 {
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sgtl5000: codec@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clock-frequency = <26000000>;
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clocks = <&clk_26M>;
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VDDA-supply = <&vdig_reg>;
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VDDIO-supply = <&vvideo_reg>;
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};
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@ -27,7 +27,7 @@ reg_backlight: fixed@0 {
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm2 0 50000 0 0>;
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pwms = <&pwm2 0 50000>;
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brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
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default-brightness-level = <10>;
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enable-gpios = <&gpio7 7 0>;
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@ -725,15 +725,15 @@ MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
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uart1 {
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pinctrl_uart1_1: uart1grp-1 {
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fsl,pins = <
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MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
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MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
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MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
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MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
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>;
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};
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pinctrl_uart1_2: uart1grp-2 {
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fsl,pins = <
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MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
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MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
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MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
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MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
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>;
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};
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@ -748,8 +748,8 @@ MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
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uart2 {
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pinctrl_uart2_1: uart2grp-1 {
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fsl,pins = <
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
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>;
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};
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@ -766,17 +766,17 @@ MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
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uart3 {
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pinctrl_uart3_1: uart3grp-1 {
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fsl,pins = <
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
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MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
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MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
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MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
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MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
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>;
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};
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pinctrl_uart3_2: uart3grp-2 {
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fsl,pins = <
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
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>;
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};
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@ -785,8 +785,8 @@ MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
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uart4 {
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pinctrl_uart4_1: uart4grp-1 {
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fsl,pins = <
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MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
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MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
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MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
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MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
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>;
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};
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};
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@ -794,8 +794,8 @@ MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
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uart5 {
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pinctrl_uart5_1: uart5grp-1 {
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fsl,pins = <
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MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
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MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
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MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
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MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
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>;
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};
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};
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@ -442,8 +442,8 @@ fec0: ethernet@400d0000 {
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compatible = "fsl,mvf600-fec";
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reg = <0x400d0000 0x1000>;
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interrupts = <0 78 0x04>;
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clocks = <&clks VF610_CLK_ENET>,
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<&clks VF610_CLK_ENET>,
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clocks = <&clks VF610_CLK_ENET0>,
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<&clks VF610_CLK_ENET0>,
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<&clks VF610_CLK_ENET>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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@ -453,8 +453,8 @@ fec1: ethernet@400d1000 {
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compatible = "fsl,mvf600-fec";
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reg = <0x400d1000 0x1000>;
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interrupts = <0 79 0x04>;
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clocks = <&clks VF610_CLK_ENET>,
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<&clks VF610_CLK_ENET>,
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clocks = <&clks VF610_CLK_ENET1>,
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<&clks VF610_CLK_ENET1>,
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<&clks VF610_CLK_ENET>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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@ -199,7 +199,8 @@ static const char *pcie_axi_sels[] = { "axi", "ahb", };
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static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
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static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
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static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
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static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *vdo_axi_sels[] = { "axi", "ahb", };
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static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
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@ -392,7 +393,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
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clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
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clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
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clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
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clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels));
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clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
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clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
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clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
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@ -183,6 +183,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
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clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
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clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
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clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
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clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
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clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
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clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
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@ -135,7 +135,7 @@
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#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
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#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
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#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
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#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
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#define MX27_INT_MSHC (NR_IRQS_LEGACY + 7)
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#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
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#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
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#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
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@ -158,6 +158,8 @@
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#define VF610_CLK_GPU_SEL 145
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#define VF610_CLK_GPU_EN 146
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#define VF610_CLK_GPU2D 147
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#define VF610_CLK_END 148
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#define VF610_CLK_ENET0 148
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#define VF610_CLK_ENET1 149
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#define VF610_CLK_END 150
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#endif /* __DT_BINDINGS_CLOCK_VF610_H */
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@ -103,15 +103,15 @@
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#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
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#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
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#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
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#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
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#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
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#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
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#define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21)
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#define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0
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#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21)
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20)
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
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#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
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#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
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#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
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