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drm/amd/pm: correct sclk/mclk dpm enablement

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Correct Polaris10 sclk/mclk dpm enablement.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-09-25 14:24:04 +08:00 committed by Alex Deucher
parent baa495f764
commit d765129a71
2 changed files with 9 additions and 3 deletions
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9
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
View file

@ -1148,7 +1148,8 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
/* enable SCLK dpm */
if (!data->sclk_dpm_key_disabled) {
if (hwmgr->chip_id == CHIP_VEGAM)
if (hwmgr->chip_id >= CHIP_POLARIS10 &&
hwmgr->chip_id <= CHIP_VEGAM)
smu7_disable_sclk_vce_handshake(hwmgr);
PP_ASSERT_WITH_CODE(
@ -1169,7 +1170,11 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
"Failed to enable MCLK DPM during DPM Start Function!",
return -EINVAL);
if (hwmgr->chip_family != CHIP_VEGAM)
if ((hwmgr->chip_family == AMDGPU_FAMILY_CI) ||
(hwmgr->chip_id == CHIP_POLARIS10) ||
(hwmgr->chip_id == CHIP_POLARIS11) ||
(hwmgr->chip_id == CHIP_POLARIS12) ||
(hwmgr->chip_id == CHIP_TONGA))
PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);

3
drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
View file

@ -2470,7 +2470,8 @@ static uint32_t polaris10_get_mac_definition(uint32_t value)
case SMU_MAX_LEVELS_MVDD:
return SMU74_MAX_LEVELS_MVDD;
case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
}
pr_warn("can't get the mac of %x\n", value);