mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 10:57:46 +00:00
ARM: SAMSUNG: Remove remaining legacy code
After refactoring suspend/resume, which was last part with dependencies on legacy code, all Kconfig symbols related to Samsung ATAGS support can be deselected and more unused code removed. This includes most of s5p-* code as well, as s5pv210 was their last user. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
parent
09ee2dac4c
commit
d78c16ccde
36 changed files with 14 additions and 2362 deletions
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
|
||||
* Jaswinder Singh <jassi.brar@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_DMA_H
|
||||
#define __MACH_DMA_H
|
||||
|
||||
/* This platform uses the common DMA API driver for PL330 */
|
||||
#include <plat/dma-pl330.h>
|
||||
|
||||
#endif /* __MACH_DMA_H */
|
|
@ -1,140 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv210/include/mach/gpio.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5PV210 - GPIO lib support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_GPIO_H
|
||||
#define __ASM_ARCH_GPIO_H __FILE__
|
||||
|
||||
/* Practically, GPIO banks up to MP03 are the configurable gpio banks */
|
||||
|
||||
/* GPIO bank sizes */
|
||||
#define S5PV210_GPIO_A0_NR (8)
|
||||
#define S5PV210_GPIO_A1_NR (4)
|
||||
#define S5PV210_GPIO_B_NR (8)
|
||||
#define S5PV210_GPIO_C0_NR (5)
|
||||
#define S5PV210_GPIO_C1_NR (5)
|
||||
#define S5PV210_GPIO_D0_NR (4)
|
||||
#define S5PV210_GPIO_D1_NR (6)
|
||||
#define S5PV210_GPIO_E0_NR (8)
|
||||
#define S5PV210_GPIO_E1_NR (5)
|
||||
#define S5PV210_GPIO_F0_NR (8)
|
||||
#define S5PV210_GPIO_F1_NR (8)
|
||||
#define S5PV210_GPIO_F2_NR (8)
|
||||
#define S5PV210_GPIO_F3_NR (6)
|
||||
#define S5PV210_GPIO_G0_NR (7)
|
||||
#define S5PV210_GPIO_G1_NR (7)
|
||||
#define S5PV210_GPIO_G2_NR (7)
|
||||
#define S5PV210_GPIO_G3_NR (7)
|
||||
#define S5PV210_GPIO_H0_NR (8)
|
||||
#define S5PV210_GPIO_H1_NR (8)
|
||||
#define S5PV210_GPIO_H2_NR (8)
|
||||
#define S5PV210_GPIO_H3_NR (8)
|
||||
#define S5PV210_GPIO_I_NR (7)
|
||||
#define S5PV210_GPIO_J0_NR (8)
|
||||
#define S5PV210_GPIO_J1_NR (6)
|
||||
#define S5PV210_GPIO_J2_NR (8)
|
||||
#define S5PV210_GPIO_J3_NR (8)
|
||||
#define S5PV210_GPIO_J4_NR (5)
|
||||
|
||||
#define S5PV210_GPIO_MP01_NR (8)
|
||||
#define S5PV210_GPIO_MP02_NR (4)
|
||||
#define S5PV210_GPIO_MP03_NR (8)
|
||||
#define S5PV210_GPIO_MP04_NR (8)
|
||||
#define S5PV210_GPIO_MP05_NR (8)
|
||||
|
||||
/* GPIO bank numbers */
|
||||
|
||||
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
|
||||
* space for debugging purposes so that any accidental
|
||||
* change from one gpio bank to another can be caught.
|
||||
*/
|
||||
|
||||
#define S5PV210_GPIO_NEXT(__gpio) \
|
||||
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
|
||||
|
||||
enum s5p_gpio_number {
|
||||
S5PV210_GPIO_A0_START = 0,
|
||||
S5PV210_GPIO_A1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_A0),
|
||||
S5PV210_GPIO_B_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_A1),
|
||||
S5PV210_GPIO_C0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_B),
|
||||
S5PV210_GPIO_C1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_C0),
|
||||
S5PV210_GPIO_D0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_C1),
|
||||
S5PV210_GPIO_D1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_D0),
|
||||
S5PV210_GPIO_E0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_D1),
|
||||
S5PV210_GPIO_E1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_E0),
|
||||
S5PV210_GPIO_F0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_E1),
|
||||
S5PV210_GPIO_F1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F0),
|
||||
S5PV210_GPIO_F2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F1),
|
||||
S5PV210_GPIO_F3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F2),
|
||||
S5PV210_GPIO_G0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F3),
|
||||
S5PV210_GPIO_G1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G0),
|
||||
S5PV210_GPIO_G2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G1),
|
||||
S5PV210_GPIO_G3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G2),
|
||||
S5PV210_GPIO_H0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G3),
|
||||
S5PV210_GPIO_H1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H0),
|
||||
S5PV210_GPIO_H2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H1),
|
||||
S5PV210_GPIO_H3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H2),
|
||||
S5PV210_GPIO_I_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H3),
|
||||
S5PV210_GPIO_J0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_I),
|
||||
S5PV210_GPIO_J1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J0),
|
||||
S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1),
|
||||
S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2),
|
||||
S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3),
|
||||
S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
|
||||
S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
|
||||
S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
|
||||
S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
|
||||
S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
|
||||
};
|
||||
|
||||
/* S5PV210 GPIO number definitions */
|
||||
#define S5PV210_GPA0(_nr) (S5PV210_GPIO_A0_START + (_nr))
|
||||
#define S5PV210_GPA1(_nr) (S5PV210_GPIO_A1_START + (_nr))
|
||||
#define S5PV210_GPB(_nr) (S5PV210_GPIO_B_START + (_nr))
|
||||
#define S5PV210_GPC0(_nr) (S5PV210_GPIO_C0_START + (_nr))
|
||||
#define S5PV210_GPC1(_nr) (S5PV210_GPIO_C1_START + (_nr))
|
||||
#define S5PV210_GPD0(_nr) (S5PV210_GPIO_D0_START + (_nr))
|
||||
#define S5PV210_GPD1(_nr) (S5PV210_GPIO_D1_START + (_nr))
|
||||
#define S5PV210_GPE0(_nr) (S5PV210_GPIO_E0_START + (_nr))
|
||||
#define S5PV210_GPE1(_nr) (S5PV210_GPIO_E1_START + (_nr))
|
||||
#define S5PV210_GPF0(_nr) (S5PV210_GPIO_F0_START + (_nr))
|
||||
#define S5PV210_GPF1(_nr) (S5PV210_GPIO_F1_START + (_nr))
|
||||
#define S5PV210_GPF2(_nr) (S5PV210_GPIO_F2_START + (_nr))
|
||||
#define S5PV210_GPF3(_nr) (S5PV210_GPIO_F3_START + (_nr))
|
||||
#define S5PV210_GPG0(_nr) (S5PV210_GPIO_G0_START + (_nr))
|
||||
#define S5PV210_GPG1(_nr) (S5PV210_GPIO_G1_START + (_nr))
|
||||
#define S5PV210_GPG2(_nr) (S5PV210_GPIO_G2_START + (_nr))
|
||||
#define S5PV210_GPG3(_nr) (S5PV210_GPIO_G3_START + (_nr))
|
||||
#define S5PV210_GPH0(_nr) (S5PV210_GPIO_H0_START + (_nr))
|
||||
#define S5PV210_GPH1(_nr) (S5PV210_GPIO_H1_START + (_nr))
|
||||
#define S5PV210_GPH2(_nr) (S5PV210_GPIO_H2_START + (_nr))
|
||||
#define S5PV210_GPH3(_nr) (S5PV210_GPIO_H3_START + (_nr))
|
||||
#define S5PV210_GPI(_nr) (S5PV210_GPIO_I_START + (_nr))
|
||||
#define S5PV210_GPJ0(_nr) (S5PV210_GPIO_J0_START + (_nr))
|
||||
#define S5PV210_GPJ1(_nr) (S5PV210_GPIO_J1_START + (_nr))
|
||||
#define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr))
|
||||
#define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr))
|
||||
#define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr))
|
||||
#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr))
|
||||
#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr))
|
||||
#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr))
|
||||
#define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr))
|
||||
#define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr))
|
||||
|
||||
/* the end of the S5PV210 specific gpios */
|
||||
#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1)
|
||||
#define S3C_GPIO_END S5PV210_GPIO_END
|
||||
|
||||
/* define the number of gpios we need to the one after the MP05() range */
|
||||
#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \
|
||||
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
|
||||
|
||||
#endif /* __ASM_ARCH_GPIO_H */
|
|
@ -1,18 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv210/include/mach/hardware.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5PV210 - Hardware support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H __FILE__
|
||||
|
||||
/* currently nothing here, placeholder */
|
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */
|
|
@ -1,137 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv210/include/mach/irqs.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5PV210 - IRQ definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IRQS_H
|
||||
#define __ASM_ARCH_IRQS_H __FILE__
|
||||
|
||||
#include <plat/irqs.h>
|
||||
|
||||
/* VIC0: System, DMA, Timer */
|
||||
|
||||
#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
|
||||
#define IRQ_BATF S5P_IRQ_VIC0(17)
|
||||
#define IRQ_MDMA S5P_IRQ_VIC0(18)
|
||||
#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
|
||||
#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
|
||||
#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
|
||||
#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
|
||||
#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
|
||||
#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
|
||||
#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
|
||||
#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
|
||||
#define IRQ_WDT S5P_IRQ_VIC0(27)
|
||||
#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
|
||||
#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
|
||||
#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
|
||||
#define IRQ_FIMC3 S5P_IRQ_VIC0(31)
|
||||
|
||||
/* VIC1: ARM, Power, Memory, Connectivity, Storage */
|
||||
|
||||
#define IRQ_PMU S5P_IRQ_VIC1(0)
|
||||
#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
|
||||
#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
|
||||
#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
|
||||
#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
|
||||
#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
|
||||
#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
|
||||
#define IRQ_ONENAND S5P_IRQ_VIC1(7)
|
||||
#define IRQ_NFC S5P_IRQ_VIC1(8)
|
||||
#define IRQ_CFCON S5P_IRQ_VIC1(9)
|
||||
#define IRQ_UART0 S5P_IRQ_VIC1(10)
|
||||
#define IRQ_UART1 S5P_IRQ_VIC1(11)
|
||||
#define IRQ_UART2 S5P_IRQ_VIC1(12)
|
||||
#define IRQ_UART3 S5P_IRQ_VIC1(13)
|
||||
#define IRQ_IIC S5P_IRQ_VIC1(14)
|
||||
#define IRQ_SPI0 S5P_IRQ_VIC1(15)
|
||||
#define IRQ_SPI1 S5P_IRQ_VIC1(16)
|
||||
#define IRQ_SPI2 S5P_IRQ_VIC1(17)
|
||||
#define IRQ_IRDA S5P_IRQ_VIC1(18)
|
||||
#define IRQ_IIC2 S5P_IRQ_VIC1(19)
|
||||
#define IRQ_IIC_HDMIPHY S5P_IRQ_VIC1(20)
|
||||
#define IRQ_HSIRX S5P_IRQ_VIC1(21)
|
||||
#define IRQ_HSITX S5P_IRQ_VIC1(22)
|
||||
#define IRQ_UHOST S5P_IRQ_VIC1(23)
|
||||
#define IRQ_OTG S5P_IRQ_VIC1(24)
|
||||
#define IRQ_MSM S5P_IRQ_VIC1(25)
|
||||
#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
|
||||
#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
|
||||
#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
|
||||
#define IRQ_MIPI_CSIS S5P_IRQ_VIC1(29)
|
||||
#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
|
||||
#define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31)
|
||||
|
||||
/* VIC2: Multimedia, Audio, Security */
|
||||
|
||||
#define IRQ_LCD0 S5P_IRQ_VIC2(0)
|
||||
#define IRQ_LCD1 S5P_IRQ_VIC2(1)
|
||||
#define IRQ_LCD2 S5P_IRQ_VIC2(2)
|
||||
#define IRQ_LCD3 S5P_IRQ_VIC2(3)
|
||||
#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
|
||||
#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
|
||||
#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
|
||||
#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
|
||||
#define IRQ_JPEG S5P_IRQ_VIC2(8)
|
||||
#define IRQ_2D S5P_IRQ_VIC2(9)
|
||||
#define IRQ_3D S5P_IRQ_VIC2(10)
|
||||
#define IRQ_MIXER S5P_IRQ_VIC2(11)
|
||||
#define IRQ_HDMI S5P_IRQ_VIC2(12)
|
||||
#define IRQ_IIC1 S5P_IRQ_VIC2(13)
|
||||
#define IRQ_MFC S5P_IRQ_VIC2(14)
|
||||
#define IRQ_SDO S5P_IRQ_VIC2(15)
|
||||
#define IRQ_I2S0 S5P_IRQ_VIC2(16)
|
||||
#define IRQ_I2S1 S5P_IRQ_VIC2(17)
|
||||
#define IRQ_I2S2 S5P_IRQ_VIC2(18)
|
||||
#define IRQ_AC97 S5P_IRQ_VIC2(19)
|
||||
#define IRQ_PCM0 S5P_IRQ_VIC2(20)
|
||||
#define IRQ_PCM1 S5P_IRQ_VIC2(21)
|
||||
#define IRQ_SPDIF S5P_IRQ_VIC2(22)
|
||||
#define IRQ_ADC S5P_IRQ_VIC2(23)
|
||||
#define IRQ_PENDN S5P_IRQ_VIC2(24)
|
||||
#define IRQ_TC IRQ_PENDN
|
||||
#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
|
||||
#define IRQ_CG S5P_IRQ_VIC2(26)
|
||||
#define IRQ_SSS_INT S5P_IRQ_VIC2(27)
|
||||
#define IRQ_SSS_HASH S5P_IRQ_VIC2(28)
|
||||
#define IRQ_PCM2 S5P_IRQ_VIC2(29)
|
||||
#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
|
||||
#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
|
||||
|
||||
/* VIC3: Etc */
|
||||
|
||||
#define IRQ_IPC S5P_IRQ_VIC3(0)
|
||||
#define IRQ_HOSTIF S5P_IRQ_VIC3(1)
|
||||
#define IRQ_HSMMC3 S5P_IRQ_VIC3(2)
|
||||
#define IRQ_CEC S5P_IRQ_VIC3(3)
|
||||
#define IRQ_TSI S5P_IRQ_VIC3(4)
|
||||
#define IRQ_MDNIE0 S5P_IRQ_VIC3(5)
|
||||
#define IRQ_MDNIE1 S5P_IRQ_VIC3(6)
|
||||
#define IRQ_MDNIE2 S5P_IRQ_VIC3(7)
|
||||
#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
|
||||
#define IRQ_VIC_END S5P_IRQ_VIC3(31)
|
||||
|
||||
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
|
||||
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
|
||||
|
||||
/* GPIO interrupt */
|
||||
#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
|
||||
#define S5P_GPIOINT_GROUP_MAXNR 22
|
||||
|
||||
/* Set the default NR_IRQS */
|
||||
#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
|
||||
|
||||
/* Compatibility */
|
||||
#define IRQ_LCD_FIFO IRQ_LCD0
|
||||
#define IRQ_LCD_VSYNC IRQ_LCD1
|
||||
#define IRQ_LCD_SYSTEM IRQ_LCD2
|
||||
#define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS
|
||||
|
||||
#endif /* ASM_ARCH_IRQS_H */
|
|
@ -1,158 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv210/include/mach/map.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5PV210 - Memory map definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MAP_H
|
||||
#define __ASM_ARCH_MAP_H __FILE__
|
||||
|
||||
#include <plat/map-base.h>
|
||||
#include <plat/map-s5p.h>
|
||||
|
||||
#define S5PV210_PA_SDRAM 0x20000000
|
||||
|
||||
#define S5PV210_PA_SROM_BANK5 0xA8000000
|
||||
|
||||
#define S5PC110_PA_ONENAND 0xB0000000
|
||||
#define S5PC110_PA_ONENAND_DMA 0xB0600000
|
||||
|
||||
#define S5PV210_PA_CHIPID 0xE0000000
|
||||
|
||||
#define S5PV210_PA_SYSCON 0xE0100000
|
||||
|
||||
#define S5PV210_PA_GPIO 0xE0200000
|
||||
|
||||
#define S5PV210_PA_SPDIF 0xE1100000
|
||||
|
||||
#define S5PV210_PA_SPI0 0xE1300000
|
||||
#define S5PV210_PA_SPI1 0xE1400000
|
||||
|
||||
#define S5PV210_PA_KEYPAD 0xE1600000
|
||||
|
||||
#define S5PV210_PA_ADC 0xE1700000
|
||||
|
||||
#define S5PV210_PA_IIC0 0xE1800000
|
||||
#define S5PV210_PA_IIC1 0xFAB00000
|
||||
#define S5PV210_PA_IIC2 0xE1A00000
|
||||
|
||||
#define S5PV210_PA_AC97 0xE2200000
|
||||
|
||||
#define S5PV210_PA_PCM0 0xE2300000
|
||||
#define S5PV210_PA_PCM1 0xE1200000
|
||||
#define S5PV210_PA_PCM2 0xE2B00000
|
||||
|
||||
#define S5PV210_PA_TIMER 0xE2500000
|
||||
#define S5PV210_PA_SYSTIMER 0xE2600000
|
||||
#define S5PV210_PA_WATCHDOG 0xE2700000
|
||||
#define S5PV210_PA_RTC 0xE2800000
|
||||
|
||||
#define S5PV210_PA_UART 0xE2900000
|
||||
|
||||
#define S5PV210_PA_SROMC 0xE8000000
|
||||
|
||||
#define S5PV210_PA_CFCON 0xE8200000
|
||||
|
||||
#define S5PV210_PA_MFC 0xF1700000
|
||||
|
||||
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
|
||||
|
||||
#define S5PV210_PA_HSOTG 0xEC000000
|
||||
#define S5PV210_PA_HSPHY 0xEC100000
|
||||
|
||||
#define S5PV210_PA_IIS0 0xEEE30000
|
||||
#define S5PV210_PA_IIS1 0xE2100000
|
||||
#define S5PV210_PA_IIS2 0xE2A00000
|
||||
|
||||
#define S5PV210_PA_DMC0 0xF0000000
|
||||
#define S5PV210_PA_DMC1 0xF1400000
|
||||
|
||||
#define S5PV210_PA_VIC0 0xF2000000
|
||||
#define S5PV210_PA_VIC1 0xF2100000
|
||||
#define S5PV210_PA_VIC2 0xF2200000
|
||||
#define S5PV210_PA_VIC3 0xF2300000
|
||||
|
||||
#define S5PV210_PA_FB 0xF8000000
|
||||
|
||||
#define S5PV210_PA_MDMA 0xFA200000
|
||||
#define S5PV210_PA_PDMA0 0xE0900000
|
||||
#define S5PV210_PA_PDMA1 0xE0A00000
|
||||
|
||||
#define S5PV210_PA_MIPI_CSIS 0xFA600000
|
||||
|
||||
#define S5PV210_PA_FIMC0 0xFB200000
|
||||
#define S5PV210_PA_FIMC1 0xFB300000
|
||||
#define S5PV210_PA_FIMC2 0xFB400000
|
||||
|
||||
#define S5PV210_PA_JPEG 0xFB600000
|
||||
|
||||
#define S5PV210_PA_SDO 0xF9000000
|
||||
#define S5PV210_PA_VP 0xF9100000
|
||||
#define S5PV210_PA_MIXER 0xF9200000
|
||||
#define S5PV210_PA_HDMI 0xFA100000
|
||||
#define S5PV210_PA_IIC_HDMIPHY 0xFA900000
|
||||
|
||||
/* Compatibiltiy Defines */
|
||||
|
||||
#define S3C_PA_FB S5PV210_PA_FB
|
||||
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
|
||||
#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
|
||||
#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
|
||||
#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
|
||||
#define S3C_PA_IIC S5PV210_PA_IIC0
|
||||
#define S3C_PA_IIC1 S5PV210_PA_IIC1
|
||||
#define S3C_PA_IIC2 S5PV210_PA_IIC2
|
||||
#define S3C_PA_RTC S5PV210_PA_RTC
|
||||
#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
|
||||
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
|
||||
#define S3C_PA_SPI0 S5PV210_PA_SPI0
|
||||
#define S3C_PA_SPI1 S5PV210_PA_SPI1
|
||||
|
||||
#define S5P_PA_CHIPID S5PV210_PA_CHIPID
|
||||
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
|
||||
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
|
||||
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
|
||||
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
|
||||
#define S5P_PA_MFC S5PV210_PA_MFC
|
||||
#define S5P_PA_IIC_HDMIPHY S5PV210_PA_IIC_HDMIPHY
|
||||
|
||||
#define S5P_PA_SDO S5PV210_PA_SDO
|
||||
#define S5P_PA_VP S5PV210_PA_VP
|
||||
#define S5P_PA_MIXER S5PV210_PA_MIXER
|
||||
#define S5P_PA_HDMI S5PV210_PA_HDMI
|
||||
|
||||
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
|
||||
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
|
||||
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
|
||||
#define S5P_PA_SROMC S5PV210_PA_SROMC
|
||||
#define S5P_PA_SYSCON S5PV210_PA_SYSCON
|
||||
#define S5P_PA_TIMER S5PV210_PA_TIMER
|
||||
|
||||
#define S5P_PA_JPEG S5PV210_PA_JPEG
|
||||
|
||||
#define SAMSUNG_PA_ADC S5PV210_PA_ADC
|
||||
#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
|
||||
#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
|
||||
#define SAMSUNG_PA_TIMER S5PV210_PA_TIMER
|
||||
|
||||
/* UART */
|
||||
|
||||
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
|
||||
|
||||
#define S3C_PA_UART S5PV210_PA_UART
|
||||
|
||||
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
|
||||
#define S5P_PA_UART0 S5P_PA_UART(0)
|
||||
#define S5P_PA_UART1 S5P_PA_UART(1)
|
||||
#define S5P_PA_UART2 S5P_PA_UART(2)
|
||||
#define S5P_PA_UART3 S5P_PA_UART(3)
|
||||
|
||||
#define S5P_SZ_UART SZ_256
|
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */
|
|
@ -1,27 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv210/include/mach/memory.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5PV210 - Memory definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
#define PLAT_PHYS_OFFSET UL(0x20000000)
|
||||
|
||||
/*
|
||||
* Sparsemem support
|
||||
* Physical memory can be located from 0x20000000 to 0x7fffffff,
|
||||
* so MAX_PHYSMEM_BITS is 31.
|
||||
*/
|
||||
|
||||
#define MAX_PHYSMEM_BITS 31
|
||||
#define SECTION_SIZE_BITS 28
|
||||
|
||||
#endif /* __ASM_ARCH_MEMORY_H */
|
|
@ -1,46 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
static inline void s3c_pm_debug_init_uart(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_prepare_irqs(void)
|
||||
{
|
||||
__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
|
||||
__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_stop_clocks(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_show_resume_irqs(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
|
||||
struct pm_uart_save *save)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_restored_gpios(void) { }
|
||||
static inline void samsung_pm_saved_gpios(void) { }
|
|
@ -13,7 +13,7 @@
|
|||
#ifndef __ASM_ARCH_REGS_CLOCK_H
|
||||
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <plat/map-base.h>
|
||||
|
||||
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
|
||||
|
||||
|
|
|
@ -1,41 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV210 - GPIO (including EINT) register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_GPIO_H
|
||||
#define __ASM_ARCH_REGS_GPIO_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00)
|
||||
#define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4))
|
||||
|
||||
#define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
|
||||
#define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4))
|
||||
|
||||
#define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00)
|
||||
#define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4))
|
||||
|
||||
#define S5PV210_EINT30PEND (S5P_VA_GPIO + 0xF40)
|
||||
#define S5P_EINT_PEND(x) (S5PV210_EINT30PEND + ((x) * 0x4))
|
||||
|
||||
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
|
||||
|
||||
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
|
||||
|
||||
#define EINT_MODE S3C_GPIO_SFN(0xf)
|
||||
|
||||
#define EINT_GPIO_0(x) S5PV210_GPH0(x)
|
||||
#define EINT_GPIO_1(x) S5PV210_GPH1(x)
|
||||
#define EINT_GPIO_2(x) S5PV210_GPH2(x)
|
||||
#define EINT_GPIO_3(x) S5PV210_GPH3(x)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_GPIO_H */
|
|
@ -1,18 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv210/include/mach/regs-irq.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5PV210 - IRQ register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_IRQ_H
|
||||
#define __ASM_ARCH_REGS_IRQ_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_IRQ_H */
|
|
@ -1,30 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv210/setup-i2c0.c
|
||||
*
|
||||
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* I2C0 GPIO configuration.
|
||||
*
|
||||
* Based on plat-s3c64xx/setup-i2c0.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
struct platform_device; /* don't need the contents */
|
||||
|
||||
#include <linux/platform_data/i2c-s3c2410.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
/*
|
||||
* FIXME: Used only by legacy code that is not used anymore,
|
||||
* but still compiled in, until all dependencies are removed.
|
||||
*/
|
||||
}
|
|
@ -6,29 +6,16 @@
|
|||
|
||||
config PLAT_SAMSUNG
|
||||
bool
|
||||
depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS
|
||||
depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_EXYNOS || ARCH_S5PV210
|
||||
default y
|
||||
select GENERIC_IRQ_CHIP
|
||||
select NO_IOPORT_MAP
|
||||
help
|
||||
Base platform code for all Samsung SoC based systems
|
||||
|
||||
config PLAT_S5P
|
||||
bool
|
||||
depends on ARCH_S5PV210
|
||||
default y
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_VIC
|
||||
select NO_IOPORT_MAP
|
||||
select PLAT_SAMSUNG
|
||||
select S3C_GPIO_TRACK
|
||||
select S5P_GPIO_DRVSTR
|
||||
help
|
||||
Base platform code for Samsung's S5P series SoC.
|
||||
|
||||
config SAMSUNG_PM
|
||||
bool
|
||||
depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM)
|
||||
depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX)
|
||||
default y
|
||||
help
|
||||
Base platform power management code for samsung code
|
||||
|
@ -64,31 +51,6 @@ config SAMSUNG_ATAGS
|
|||
|
||||
if SAMSUNG_ATAGS
|
||||
|
||||
# options for IRQ support
|
||||
|
||||
config S5P_IRQ
|
||||
def_bool ARCH_S5PV210
|
||||
help
|
||||
Support common interrupt part for ARCH_S5P SoCs
|
||||
|
||||
config S5P_EXT_INT
|
||||
bool
|
||||
help
|
||||
Use the external interrupts (other than GPIO interrupts.)
|
||||
|
||||
config S5P_GPIO_INT
|
||||
bool
|
||||
help
|
||||
Common code for the GPIO interrupts (other than external interrupts.)
|
||||
|
||||
# options for gpio configuration support
|
||||
|
||||
config S5P_GPIO_DRVSTR
|
||||
bool
|
||||
help
|
||||
Internal configuration to get and set correct GPIO driver strength
|
||||
helper
|
||||
|
||||
config SAMSUNG_GPIO_EXTRA
|
||||
int "Number of additional GPIO pins"
|
||||
default 128 if SAMSUNG_GPIO_EXTRA128
|
||||
|
@ -120,12 +82,6 @@ config S3C_GPIO_TRACK
|
|||
Internal configuration option to enable the s3c specific gpio
|
||||
chip tracking if the platform requires it.
|
||||
|
||||
# uart options
|
||||
|
||||
config S5P_DEV_UART
|
||||
def_bool y
|
||||
depends on ARCH_S5PV210
|
||||
|
||||
# ADC driver
|
||||
|
||||
config S3C_ADC
|
||||
|
@ -283,66 +239,6 @@ config SAMSUNG_DEV_BACKLIGHT
|
|||
help
|
||||
Compile in platform device definition LCD backlight with PWM Timer
|
||||
|
||||
config S5P_DEV_CSIS0
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for MIPI-CSIS channel 0
|
||||
|
||||
config S5P_DEV_CSIS1
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for MIPI-CSIS channel 1
|
||||
|
||||
config S5P_DEV_FIMC0
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for FIMC controller 0
|
||||
|
||||
config S5P_DEV_FIMC1
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for FIMC controller 1
|
||||
|
||||
config S5P_DEV_FIMC2
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for FIMC controller 2
|
||||
|
||||
config S5P_DEV_FIMC3
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for FIMC controller 3
|
||||
|
||||
config S5P_DEV_FIMD0
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for FIMD controller 0
|
||||
|
||||
config S5P_DEV_G2D
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for G2D device
|
||||
|
||||
config S5P_DEV_I2C_HDMIPHY
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for I2C HDMIPHY controller
|
||||
|
||||
config S5P_DEV_JPEG
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for JPEG codec
|
||||
|
||||
config S5P_DEV_ONENAND
|
||||
bool
|
||||
help
|
||||
Compile in platform device definition for OneNAND controller
|
||||
|
||||
config S5P_DEV_TV
|
||||
bool
|
||||
help
|
||||
Compile in platform device definition for TV interface
|
||||
|
||||
config S3C24XX_PWM
|
||||
bool "PWM device support"
|
||||
select PWM
|
||||
|
@ -363,12 +259,6 @@ config S3C_DMA
|
|||
help
|
||||
Internal configuration for S3C DMA core
|
||||
|
||||
config S5P_IRQ_PM
|
||||
bool
|
||||
default y if S5P_PM
|
||||
help
|
||||
Legacy IRQ power management for S5P platforms
|
||||
|
||||
config SAMSUNG_PM_GPIO
|
||||
bool
|
||||
default y if GPIO_SAMSUNG && PM
|
||||
|
@ -451,17 +341,6 @@ config SAMSUNG_WDT_RESET
|
|||
Compile support for system restart by triggering watchdog reset.
|
||||
Used on SoCs that do not provide dedicated reset control.
|
||||
|
||||
config S5P_PM
|
||||
bool
|
||||
help
|
||||
Common code for power management support on S5P and newer SoCs
|
||||
|
||||
config S5P_SLEEP
|
||||
bool
|
||||
help
|
||||
Internal config node to apply common S5P sleep management code.
|
||||
Can be selected by S5P and newer SoCs with similar sleep procedure.
|
||||
|
||||
config DEBUG_S3C_UART
|
||||
depends on PLAT_SAMSUNG
|
||||
int
|
||||
|
|
|
@ -15,10 +15,6 @@ obj- :=
|
|||
|
||||
obj-y += init.o cpu.o
|
||||
|
||||
obj-$(CONFIG_S5P_IRQ) += s5p-irq.o
|
||||
obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o
|
||||
obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o
|
||||
|
||||
# ADC
|
||||
|
||||
obj-$(CONFIG_S3C_ADC) += adc.o
|
||||
|
@ -30,7 +26,6 @@ obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o
|
|||
obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o
|
||||
obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o
|
||||
obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o
|
||||
obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o
|
||||
|
||||
obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
|
||||
|
||||
|
@ -52,7 +47,3 @@ obj-$(CONFIG_SAMSUNG_PM_DEBUG) += pm-debug.o
|
|||
|
||||
obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
|
||||
obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
|
||||
|
||||
obj-$(CONFIG_S5P_PM) += s5p-pm.o
|
||||
obj-$(CONFIG_S5P_IRQ_PM) += s5p-irq-pm.o
|
||||
obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
|
||||
#include <plat/map-base.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
|
|
|
@ -53,7 +53,6 @@
|
|||
#include <linux/platform_data/ata-samsung_cf.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/fb-s3c2410.h>
|
||||
#include <plat/hdmi.h>
|
||||
#include <linux/platform_data/hwmon-s3c.h>
|
||||
#include <linux/platform_data/i2c-s3c2410.h>
|
||||
#include <plat/keypad.h>
|
||||
|
@ -145,23 +144,6 @@ struct platform_device s3c_device_camif = {
|
|||
};
|
||||
#endif /* CONFIG_CPU_S3C2440 */
|
||||
|
||||
/* ASOC DMA */
|
||||
|
||||
#ifdef CONFIG_PLAT_S5P
|
||||
static struct resource samsung_asoc_idma_resource = DEFINE_RES_IRQ(IRQ_I2S0);
|
||||
|
||||
struct platform_device samsung_asoc_idma = {
|
||||
.name = "samsung-idma",
|
||||
.id = -1,
|
||||
.num_resources = 1,
|
||||
.resource = &samsung_asoc_idma_resource,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
/* FB */
|
||||
|
||||
#ifdef CONFIG_S3C_DEV_FB
|
||||
|
@ -190,151 +172,6 @@ void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
|
|||
}
|
||||
#endif /* CONFIG_S3C_DEV_FB */
|
||||
|
||||
/* FIMC */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_FIMC0
|
||||
static struct resource s5p_fimc0_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_FIMC0),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_fimc0 = {
|
||||
.name = "s5p-fimc",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5p_fimc0_resource),
|
||||
.resource = s5p_fimc0_resource,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_fimc_md = {
|
||||
.name = "s5p-fimc-md",
|
||||
.id = -1,
|
||||
};
|
||||
#endif /* CONFIG_S5P_DEV_FIMC0 */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_FIMC1
|
||||
static struct resource s5p_fimc1_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_FIMC1),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_fimc1 = {
|
||||
.name = "s5p-fimc",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(s5p_fimc1_resource),
|
||||
.resource = s5p_fimc1_resource,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_S5P_DEV_FIMC1 */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_FIMC2
|
||||
static struct resource s5p_fimc2_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_FIMC2),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_fimc2 = {
|
||||
.name = "s5p-fimc",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(s5p_fimc2_resource),
|
||||
.resource = s5p_fimc2_resource,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_S5P_DEV_FIMC2 */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_FIMC3
|
||||
static struct resource s5p_fimc3_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_FIMC3),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_fimc3 = {
|
||||
.name = "s5p-fimc",
|
||||
.id = 3,
|
||||
.num_resources = ARRAY_SIZE(s5p_fimc3_resource),
|
||||
.resource = s5p_fimc3_resource,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_S5P_DEV_FIMC3 */
|
||||
|
||||
/* G2D */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_G2D
|
||||
static struct resource s5p_g2d_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_2D),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_g2d = {
|
||||
.name = "s5p-g2d",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5p_g2d_resource),
|
||||
.resource = s5p_g2d_resource,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_S5P_DEV_G2D */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_JPEG
|
||||
static struct resource s5p_jpeg_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_JPEG),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_jpeg = {
|
||||
.name = "s5p-jpeg",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5p_jpeg_resource),
|
||||
.resource = s5p_jpeg_resource,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_S5P_DEV_JPEG */
|
||||
|
||||
/* FIMD0 */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_FIMD0
|
||||
static struct resource s5p_fimd0_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
|
||||
[1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
|
||||
[2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
|
||||
[3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_fimd0 = {
|
||||
.name = "s5p-fb",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5p_fimd0_resource),
|
||||
.resource = s5p_fimd0_resource,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
|
||||
{
|
||||
s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
|
||||
&s5p_device_fimd0);
|
||||
}
|
||||
#endif /* CONFIG_S5P_DEV_FIMD0 */
|
||||
|
||||
/* HWMON */
|
||||
|
||||
#ifdef CONFIG_S3C_DEV_HWMON
|
||||
|
@ -722,60 +559,6 @@ void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
|
|||
}
|
||||
#endif /* CONFIG_S3C_DEV_I2C7 */
|
||||
|
||||
/* I2C HDMIPHY */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
|
||||
static struct resource s5p_i2c_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_i2c_hdmiphy = {
|
||||
.name = "s3c2440-hdmiphy-i2c",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5p_i2c_resource),
|
||||
.resource = s5p_i2c_resource,
|
||||
};
|
||||
|
||||
void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
|
||||
{
|
||||
struct s3c2410_platform_i2c *npd;
|
||||
|
||||
if (!pd) {
|
||||
pd = &default_i2c_data;
|
||||
|
||||
if (soc_is_s5pv210())
|
||||
pd->bus_num = 3;
|
||||
else
|
||||
pd->bus_num = 0;
|
||||
}
|
||||
|
||||
npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
|
||||
&s5p_device_i2c_hdmiphy);
|
||||
}
|
||||
|
||||
static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
|
||||
|
||||
void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
|
||||
struct i2c_board_info *mhl_info, int mhl_bus)
|
||||
{
|
||||
struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
|
||||
|
||||
if (soc_is_s5pv210())
|
||||
pd->hdmiphy_bus = 3;
|
||||
else
|
||||
pd->hdmiphy_bus = 0;
|
||||
|
||||
pd->hdmiphy_info = hdmiphy_info;
|
||||
pd->mhl_info = mhl_info;
|
||||
pd->mhl_bus = mhl_bus;
|
||||
|
||||
s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
|
||||
&s5p_device_hdmi);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
|
||||
|
||||
/* I2S */
|
||||
|
||||
#ifdef CONFIG_PLAT_S3C24XX
|
||||
|
@ -879,36 +662,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
|
|||
}
|
||||
#endif /* CONFIG_PLAT_S3C24XX */
|
||||
|
||||
/* MIPI CSIS */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_CSIS0
|
||||
static struct resource s5p_mipi_csis0_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_mipi_csis0 = {
|
||||
.name = "s5p-mipi-csis",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
|
||||
.resource = s5p_mipi_csis0_resource,
|
||||
};
|
||||
#endif /* CONFIG_S5P_DEV_CSIS0 */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_CSIS1
|
||||
static struct resource s5p_mipi_csis1_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_mipi_csis1 = {
|
||||
.name = "s5p-mipi-csis",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
|
||||
.resource = s5p_mipi_csis1_resource,
|
||||
};
|
||||
#endif
|
||||
|
||||
/* NAND */
|
||||
|
||||
#ifdef CONFIG_S3C_DEV_NAND
|
||||
|
@ -1052,43 +805,6 @@ void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
|
|||
}
|
||||
#endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_ONENAND
|
||||
static struct resource s5p_onenand_resources[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
|
||||
[1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
|
||||
[2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_onenand = {
|
||||
.name = "s5pc110-onenand",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5p_onenand_resources),
|
||||
.resource = s5p_onenand_resources,
|
||||
};
|
||||
#endif /* CONFIG_S5P_DEV_ONENAND */
|
||||
|
||||
/* PMU */
|
||||
|
||||
#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
|
||||
static struct resource s5p_pmu_resource[] = {
|
||||
DEFINE_RES_IRQ(IRQ_PMU)
|
||||
};
|
||||
|
||||
static struct platform_device s5p_device_pmu = {
|
||||
.name = "arm-pmu",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5p_pmu_resource),
|
||||
.resource = s5p_pmu_resource,
|
||||
};
|
||||
|
||||
static int __init s5p_pmu_init(void)
|
||||
{
|
||||
platform_device_register(&s5p_device_pmu);
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(s5p_pmu_init);
|
||||
#endif /* CONFIG_PLAT_S5P */
|
||||
|
||||
/* PWM Timer */
|
||||
|
||||
#ifdef CONFIG_SAMSUNG_DEV_PWM
|
||||
|
@ -1251,52 +967,6 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
|
|||
}
|
||||
#endif /* CONFIG_SAMSUNG_DEV_TS */
|
||||
|
||||
/* TV */
|
||||
|
||||
#ifdef CONFIG_S5P_DEV_TV
|
||||
|
||||
static struct resource s5p_hdmi_resources[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_HDMI),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_hdmi = {
|
||||
.name = "s5p-hdmi",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5p_hdmi_resources),
|
||||
.resource = s5p_hdmi_resources,
|
||||
};
|
||||
|
||||
static struct resource s5p_sdo_resources[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_SDO),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_sdo = {
|
||||
.name = "s5p-sdo",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5p_sdo_resources),
|
||||
.resource = s5p_sdo_resources,
|
||||
};
|
||||
|
||||
static struct resource s5p_mixer_resources[] = {
|
||||
[0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
|
||||
[1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
|
||||
[2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_mixer = {
|
||||
.name = "s5p-mixer",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5p_mixer_resources),
|
||||
.resource = s5p_mixer_resources,
|
||||
.dev = {
|
||||
.dma_mask = &samsung_device_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
}
|
||||
};
|
||||
#endif /* CONFIG_S5P_DEV_TV */
|
||||
|
||||
/* USB */
|
||||
|
||||
#ifdef CONFIG_S3C_DEV_USB_HOST
|
||||
|
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* S5P series camera interface helper functions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_SAMSUNG_CAMPORT_H_
|
||||
#define __PLAT_SAMSUNG_CAMPORT_H_ __FILE__
|
||||
|
||||
enum s5p_camport_id {
|
||||
S5P_CAMPORT_A,
|
||||
S5P_CAMPORT_B,
|
||||
};
|
||||
|
||||
/*
|
||||
* The helper functions to configure GPIO for the camera parallel bus.
|
||||
* The camera port can be multiplexed with any FIMC entity, even multiple
|
||||
* FIMC entities are allowed to be attached to a single port simultaneously.
|
||||
* These functions are to be used in the board setup code.
|
||||
*/
|
||||
int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
|
||||
int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
|
||||
|
||||
#endif /* __PLAT_SAMSUNG_CAMPORT_H */
|
|
@ -47,7 +47,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
|
|||
IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
|
||||
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
|
||||
|
@ -76,12 +75,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
|
|||
# define soc_is_s3c64xx() 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_S5PV210)
|
||||
# define soc_is_s5pv210() is_samsung_s5pv210()
|
||||
#else
|
||||
# define soc_is_s5pv210() 0
|
||||
#endif
|
||||
|
||||
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
|
||||
|
||||
#ifndef KHZ
|
||||
|
@ -117,12 +110,9 @@ extern void s3c_init_cpu(unsigned long idcode,
|
|||
|
||||
/* core initialisation functions */
|
||||
|
||||
extern void s5p_init_irq(u32 *vic, u32 num_vic);
|
||||
|
||||
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
|
||||
|
||||
extern void s3c64xx_init_cpu(void);
|
||||
extern void s5p_init_cpu(void __iomem *cpuid_addr);
|
||||
|
||||
extern unsigned int samsung_rev(void);
|
||||
|
||||
|
@ -150,6 +140,4 @@ extern struct bus_type s3c2442_subsys;
|
|||
extern struct bus_type s3c2443_subsys;
|
||||
extern struct bus_type s3c6410_subsys;
|
||||
|
||||
extern void (*s5pc1xx_idle)(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -25,9 +25,6 @@ struct s3c24xx_uart_resources {
|
|||
|
||||
extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
|
||||
extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
|
||||
extern struct s3c24xx_uart_resources s5p_uart_resources[];
|
||||
extern struct s3c24xx_uart_resources exynos4_uart_resources[];
|
||||
extern struct s3c24xx_uart_resources exynos5_uart_resources[];
|
||||
|
||||
extern struct platform_device *s3c24xx_uart_devs[];
|
||||
extern struct platform_device *s3c24xx_uart_src[];
|
||||
|
@ -75,45 +72,6 @@ extern struct platform_device s3c_device_usb_hsotg;
|
|||
extern struct platform_device s3c_device_usb_hsudc;
|
||||
extern struct platform_device s3c_device_wdt;
|
||||
|
||||
extern struct platform_device s5p_device_fimc0;
|
||||
extern struct platform_device s5p_device_fimc1;
|
||||
extern struct platform_device s5p_device_fimc2;
|
||||
extern struct platform_device s5p_device_fimc3;
|
||||
extern struct platform_device s5p_device_fimc_md;
|
||||
extern struct platform_device s5p_device_jpeg;
|
||||
extern struct platform_device s5p_device_g2d;
|
||||
extern struct platform_device s5p_device_fimd0;
|
||||
extern struct platform_device s5p_device_hdmi;
|
||||
extern struct platform_device s5p_device_i2c_hdmiphy;
|
||||
extern struct platform_device s5p_device_mfc;
|
||||
extern struct platform_device s5p_device_mfc_l;
|
||||
extern struct platform_device s5p_device_mfc_r;
|
||||
extern struct platform_device s5p_device_mipi_csis0;
|
||||
extern struct platform_device s5p_device_mipi_csis1;
|
||||
extern struct platform_device s5p_device_mixer;
|
||||
extern struct platform_device s5p_device_onenand;
|
||||
extern struct platform_device s5p_device_sdo;
|
||||
|
||||
extern struct platform_device s5pv210_device_ac97;
|
||||
extern struct platform_device s5pv210_device_iis0;
|
||||
extern struct platform_device s5pv210_device_iis1;
|
||||
extern struct platform_device s5pv210_device_iis2;
|
||||
extern struct platform_device s5pv210_device_pcm0;
|
||||
extern struct platform_device s5pv210_device_pcm1;
|
||||
extern struct platform_device s5pv210_device_pcm2;
|
||||
extern struct platform_device s5pv210_device_spdif;
|
||||
|
||||
extern struct platform_device exynos4_device_ac97;
|
||||
extern struct platform_device exynos4_device_ahci;
|
||||
extern struct platform_device exynos4_device_i2s0;
|
||||
extern struct platform_device exynos4_device_i2s1;
|
||||
extern struct platform_device exynos4_device_i2s2;
|
||||
extern struct platform_device exynos4_device_ohci;
|
||||
extern struct platform_device exynos4_device_pcm0;
|
||||
extern struct platform_device exynos4_device_pcm1;
|
||||
extern struct platform_device exynos4_device_pcm2;
|
||||
extern struct platform_device exynos4_device_spdif;
|
||||
|
||||
extern struct platform_device samsung_asoc_idma;
|
||||
extern struct platform_device samsung_device_keypad;
|
||||
extern struct platform_device samsung_device_pwm;
|
||||
|
|
|
@ -26,19 +26,4 @@ static inline void s3c_fb_setname(char *name)
|
|||
#endif
|
||||
}
|
||||
|
||||
/* Re-define device name depending on support. */
|
||||
static inline void s5p_fb_setname(int id, char *name)
|
||||
{
|
||||
switch (id) {
|
||||
#ifdef CONFIG_S5P_DEV_FIMD0
|
||||
case 0:
|
||||
s5p_device_fimd0.name = name;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __ASM_PLAT_FB_CORE_H */
|
||||
|
|
|
@ -25,14 +25,6 @@
|
|||
*/
|
||||
extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
|
||||
|
||||
/**
|
||||
* s5p_fimd0_set_platdata() - Setup the FB device with platform data.
|
||||
* @pd: The platform data to set. The data is copied from the passed structure
|
||||
* so the machine data can mark the data __initdata so that any unused
|
||||
* machines will end up dumping their data at runtime.
|
||||
*/
|
||||
extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
|
||||
|
||||
/**
|
||||
* s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
|
||||
*
|
||||
|
@ -40,18 +32,4 @@ extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
|
|||
*/
|
||||
extern void s3c64xx_fb_gpio_setup_24bpp(void);
|
||||
|
||||
/**
|
||||
* s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD
|
||||
*
|
||||
* Initialise the GPIO for an 24bpp LCD display on the RGB interface.
|
||||
*/
|
||||
extern void s5pv210_fb_gpio_setup_24bpp(void);
|
||||
|
||||
/**
|
||||
* exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
|
||||
*
|
||||
* Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
|
||||
*/
|
||||
extern void exynos4_fimd0_gpio_setup_24bpp(void);
|
||||
|
||||
#endif /* __PLAT_S3C_FB_H */
|
||||
|
|
|
@ -1,51 +0,0 @@
|
|||
/*
|
||||
* arch/arm/plat-samsung/include/plat/fimc-core.h
|
||||
*
|
||||
* Copyright 2010 Samsung Electronics Co., Ltd.
|
||||
* Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
*
|
||||
* Samsung camera interface driver core functions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_PLAT_FIMC_CORE_H
|
||||
#define __ASM_PLAT_FIMC_CORE_H __FILE__
|
||||
|
||||
/*
|
||||
* These functions are only for use with the core support code, such as
|
||||
* the CPU-specific initialization code.
|
||||
*/
|
||||
|
||||
/* Re-define device name to differentiate the subsystem in various SoCs. */
|
||||
static inline void s3c_fimc_setname(int id, char *name)
|
||||
{
|
||||
switch (id) {
|
||||
#ifdef CONFIG_S5P_DEV_FIMC0
|
||||
case 0:
|
||||
s5p_device_fimc0.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S5P_DEV_FIMC1
|
||||
case 1:
|
||||
s5p_device_fimc1.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S5P_DEV_FIMC2
|
||||
case 2:
|
||||
s5p_device_fimc2.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S5P_DEV_FIMC3
|
||||
case 3:
|
||||
s5p_device_fimc3.name = name;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __ASM_PLAT_FIMC_CORE_H */
|
|
@ -27,7 +27,6 @@
|
|||
#include <linux/types.h>
|
||||
|
||||
typedef unsigned int __bitwise__ samsung_gpio_pull_t;
|
||||
typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
|
||||
|
||||
/* forward declaration if gpio-core.h hasn't been included */
|
||||
struct samsung_gpio_chip;
|
||||
|
@ -180,67 +179,4 @@ static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
|
|||
return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
/* Define values for the drvstr available for each gpio pin.
|
||||
*
|
||||
* These values control the value of the output signal driver strength,
|
||||
* configurable on most pins on the S5P series.
|
||||
*/
|
||||
#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x0)
|
||||
#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x2)
|
||||
#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x1)
|
||||
#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x3)
|
||||
|
||||
/**
|
||||
* s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin
|
||||
* @pin: The pin number to get the settings for
|
||||
*
|
||||
* Read the driver streght value for the specified pin.
|
||||
*/
|
||||
extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
|
||||
|
||||
/**
|
||||
* s3c_gpio_set_drvstr() - set the driver streght value of a gpio pin
|
||||
* @pin: The pin number to configure the driver streght value
|
||||
* @drvstr: The new value of the driver strength
|
||||
*
|
||||
* This function sets the driver strength value for the specified pin.
|
||||
* It will return 0 if successful, or a negative error code if the pin
|
||||
* cannot support the requested setting.
|
||||
*/
|
||||
extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
|
||||
|
||||
/**
|
||||
* s5p_register_gpio_interrupt() - register interrupt support for a gpio group
|
||||
* @pin: The pin number from the group to be registered
|
||||
*
|
||||
* This function registers gpio interrupt support for the group that the
|
||||
* specified pin belongs to.
|
||||
*
|
||||
* The total number of gpio pins is quite large ob s5p series. Registering
|
||||
* irq support for all of them would be a resource waste. Because of that the
|
||||
* interrupt support for standard gpio pins is registered dynamically.
|
||||
*
|
||||
* It will return the irq number of the interrupt that has been registered
|
||||
* or -ENOMEM if no more gpio interrupts can be registered. It is allowed
|
||||
* to call this function more than once for the same gpio group (the group
|
||||
* will be registered only once).
|
||||
*/
|
||||
extern int s5p_register_gpio_interrupt(int pin);
|
||||
|
||||
/** s5p_register_gpioint_bank() - add gpio bank for further gpio interrupt
|
||||
* registration (see s5p_register_gpio_interrupt function)
|
||||
* @chain_irq: chained irq number for the gpio int handler for this bank
|
||||
* @start: start gpio group number of this bank
|
||||
* @nr_groups: number of gpio groups handled by this bank
|
||||
*
|
||||
* This functions registers initial information about gpio banks that
|
||||
* can be later used by the s5p_register_gpio_interrupt() function to
|
||||
* enable support for gpio interrupt for particular gpio group.
|
||||
*/
|
||||
#ifdef CONFIG_S5P_GPIO_INT
|
||||
extern int s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups);
|
||||
#else
|
||||
#define s5p_register_gpioint_bank(chain_irq, start, nr_groups) do { } while (0)
|
||||
#endif
|
||||
|
||||
#endif /* __PLAT_GPIO_CFG_H */
|
||||
|
|
|
@ -1,16 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics Co.Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_SAMSUNG_HDMI_H
|
||||
#define __PLAT_SAMSUNG_HDMI_H __FILE__
|
||||
|
||||
extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
|
||||
struct i2c_board_info *mhl_info, int mhl_bus);
|
||||
|
||||
#endif /* __PLAT_SAMSUNG_HDMI_H */
|
|
@ -1,72 +0,0 @@
|
|||
/* linux/arch/arm/plat-samsung/include/plat/irqs.h
|
||||
*
|
||||
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5P Common IRQ support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_SAMSUNG_IRQS_H
|
||||
#define __PLAT_SAMSUNG_IRQS_H __FILE__
|
||||
|
||||
/* we keep the first set of CPU IRQs out of the range of
|
||||
* the ISA space, so that the PC104 has them to itself
|
||||
* and we don't end up having to do horrible things to the
|
||||
* standard ISA drivers....
|
||||
*
|
||||
* note, since we're using the VICs, our start must be a
|
||||
* mulitple of 32 to allow the common code to work
|
||||
*/
|
||||
|
||||
#define S5P_IRQ_OFFSET (32)
|
||||
|
||||
#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
|
||||
|
||||
#define S5P_VIC0_BASE S5P_IRQ(0)
|
||||
#define S5P_VIC1_BASE S5P_IRQ(32)
|
||||
#define S5P_VIC2_BASE S5P_IRQ(64)
|
||||
#define S5P_VIC3_BASE S5P_IRQ(96)
|
||||
|
||||
#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
|
||||
|
||||
#define IRQ_VIC0_BASE S5P_VIC0_BASE
|
||||
#define IRQ_VIC1_BASE S5P_VIC1_BASE
|
||||
#define IRQ_VIC2_BASE S5P_VIC2_BASE
|
||||
|
||||
/* VIC based IRQs */
|
||||
|
||||
#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
|
||||
#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
|
||||
#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
|
||||
#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
|
||||
|
||||
#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
|
||||
: ((x) - 16 + S5P_EINT_BASE2))
|
||||
|
||||
#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
|
||||
((irq) - S5P_EINT_BASE1) : \
|
||||
((irq) + 16 - S5P_EINT_BASE2))
|
||||
|
||||
#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
|
||||
|
||||
/* Typically only a few gpio chips require gpio interrupt support.
|
||||
To avoid memory waste irq descriptors are allocated only for
|
||||
S5P_GPIOINT_GROUP_COUNT chips, each with total number of
|
||||
S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
|
||||
to any gpio chip with the s5p_register_gpio_interrupt() function */
|
||||
#define S5P_GPIOINT_GROUP_COUNT 4
|
||||
#define S5P_GPIOINT_GROUP_SIZE 8
|
||||
#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
|
||||
|
||||
/* IRQ types common for all s5p platforms */
|
||||
#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
|
||||
#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
|
||||
#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
|
||||
#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
|
||||
#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
|
||||
|
||||
#endif /* __PLAT_SAMSUNG_IRQS_H */
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics Co.Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_SAMSUNG_MFC_H
|
||||
#define __PLAT_SAMSUNG_MFC_H __FILE__
|
||||
|
||||
struct s5p_mfc_dt_meminfo {
|
||||
unsigned long loff;
|
||||
unsigned long lsize;
|
||||
unsigned long roff;
|
||||
unsigned long rsize;
|
||||
char *compatible;
|
||||
};
|
||||
|
||||
/**
|
||||
* s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
|
||||
* @rbase: base address for MFC 'right' memory interface
|
||||
* @rsize: size of the memory reserved for MFC 'right' interface
|
||||
* @lbase: base address for MFC 'left' memory interface
|
||||
* @lsize: size of the memory reserved for MFC 'left' interface
|
||||
*
|
||||
* This function reserves system memory for both MFC device memory
|
||||
* interfaces and registers it to respective struct device entries as
|
||||
* coherent memory.
|
||||
*/
|
||||
void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
|
||||
phys_addr_t lbase, unsigned int lsize);
|
||||
|
||||
#endif /* __PLAT_SAMSUNG_MFC_H */
|
|
@ -57,14 +57,6 @@ extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
|
|||
extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
|
||||
extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
|
||||
extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
|
||||
extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
|
||||
extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
|
||||
extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
|
||||
extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
|
||||
extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
|
||||
extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
|
||||
extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
|
||||
extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
|
||||
|
||||
/* S3C2416 SDHCI setup */
|
||||
|
||||
|
@ -144,45 +136,6 @@ static inline void s3c6400_default_sdhci2(void) { }
|
|||
|
||||
#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
|
||||
|
||||
/* S5PV210 SDHCI setup */
|
||||
|
||||
#ifdef CONFIG_S5PV210_SETUP_SDHCI
|
||||
static inline void s5pv210_default_sdhci0(void)
|
||||
{
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC
|
||||
s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void s5pv210_default_sdhci1(void)
|
||||
{
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC1
|
||||
s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void s5pv210_default_sdhci2(void)
|
||||
{
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC2
|
||||
s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void s5pv210_default_sdhci3(void)
|
||||
{
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC3
|
||||
s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
|
||||
#endif
|
||||
}
|
||||
|
||||
#else
|
||||
static inline void s5pv210_default_sdhci0(void) { }
|
||||
static inline void s5pv210_default_sdhci1(void) { }
|
||||
static inline void s5pv210_default_sdhci2(void) { }
|
||||
static inline void s5pv210_default_sdhci3(void) { }
|
||||
|
||||
#endif /* CONFIG_S5PV210_SETUP_SDHCI */
|
||||
|
||||
static inline void s3c_sdhci_setname(int id, char *name)
|
||||
{
|
||||
switch (id) {
|
||||
|
|
|
@ -1,44 +0,0 @@
|
|||
/*
|
||||
* arch/arm/plat-samsung/include/plat/tv.h
|
||||
*
|
||||
* Copyright 2011 Samsung Electronics Co., Ltd.
|
||||
* Tomasz Stanislawski <t.stanislaws@samsung.com>
|
||||
*
|
||||
* Samsung TV driver core functions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_PLAT_TV_H
|
||||
#define __SAMSUNG_PLAT_TV_H __FILE__
|
||||
|
||||
/*
|
||||
* These functions are only for use with the core support code, such as
|
||||
* the CPU-specific initialization code.
|
||||
*/
|
||||
|
||||
/* Re-define device name to differentiate the subsystem in various SoCs. */
|
||||
static inline void s5p_hdmi_setname(char *name)
|
||||
{
|
||||
#ifdef CONFIG_S5P_DEV_TV
|
||||
s5p_device_hdmi.name = name;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void s5p_mixer_setname(char *name)
|
||||
{
|
||||
#ifdef CONFIG_S5P_DEV_TV
|
||||
s5p_device_mixer.name = name;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void s5p_sdo_setname(char *name)
|
||||
{
|
||||
#ifdef CONFIG_S5P_DEV_TV
|
||||
s5p_device_sdo.name = name;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* __SAMSUNG_PLAT_TV_H */
|
|
@ -196,7 +196,7 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
|
|||
.resume = samsung_gpio_pm_2bit_resume,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
|
||||
#if defined(CONFIG_ARCH_S3C64XX)
|
||||
static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
|
||||
{
|
||||
chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
|
||||
|
@ -306,7 +306,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
|
|||
.save = samsung_gpio_pm_4bit_save,
|
||||
.resume = samsung_gpio_pm_4bit_resume,
|
||||
};
|
||||
#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
|
||||
#endif /* CONFIG_ARCH_S3C64XX */
|
||||
|
||||
/**
|
||||
* samsung_pm_save_gpio() - save gpio chip data for suspend
|
||||
|
|
|
@ -17,56 +17,16 @@
|
|||
#include <linux/of_fdt.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#ifdef CONFIG_SAMSUNG_ATAGS
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <plat/devs.h>
|
||||
|
||||
static struct resource s5p_mfc_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_MFC),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_mfc = {
|
||||
.name = "s5p-mfc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5p_mfc_resource),
|
||||
.resource = s5p_mfc_resource,
|
||||
};
|
||||
|
||||
/*
|
||||
* MFC hardware has 2 memory interfaces which are modelled as two separate
|
||||
* platform devices to let dma-mapping distinguish between them.
|
||||
*
|
||||
* MFC parent device (s5p_device_mfc) must be registered before memory
|
||||
* interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
|
||||
*/
|
||||
|
||||
struct platform_device s5p_device_mfc_l = {
|
||||
.name = "s5p-mfc-l",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.parent = &s5p_device_mfc.dev,
|
||||
.dma_mask = &s5p_device_mfc_l.dev.coherent_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_mfc_r = {
|
||||
.name = "s5p-mfc-r",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.parent = &s5p_device_mfc.dev,
|
||||
.dma_mask = &s5p_device_mfc_r.dev.coherent_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
#else
|
||||
static struct platform_device s5p_device_mfc_l;
|
||||
static struct platform_device s5p_device_mfc_r;
|
||||
#endif
|
||||
|
||||
struct s5p_mfc_dt_meminfo {
|
||||
unsigned long loff;
|
||||
unsigned long lsize;
|
||||
unsigned long roff;
|
||||
unsigned long rsize;
|
||||
char *compatible;
|
||||
};
|
||||
|
||||
struct s5p_mfc_reserved_mem {
|
||||
phys_addr_t base;
|
||||
|
@ -77,7 +37,7 @@ struct s5p_mfc_reserved_mem {
|
|||
static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
|
||||
|
||||
|
||||
void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
|
||||
static void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
|
||||
phys_addr_t lbase, unsigned int lsize)
|
||||
{
|
||||
int i;
|
||||
|
@ -100,28 +60,6 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SAMSUNG_ATAGS
|
||||
static int __init s5p_mfc_memory_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
|
||||
struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
|
||||
if (!area->base)
|
||||
continue;
|
||||
|
||||
if (dma_declare_coherent_memory(area->dev, area->base,
|
||||
area->base, area->size,
|
||||
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
|
||||
printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
|
||||
area->size, (unsigned long) area->base);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
device_initcall(s5p_mfc_memory_init);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
|
||||
int depth, void *data)
|
||||
{
|
||||
|
@ -154,4 +92,3 @@ int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
|
|||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -1,88 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2009,2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* Base S5P UART resource and device definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
/* Serial port registrations */
|
||||
|
||||
static struct resource s5p_uart0_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_UART0, S5P_SZ_UART),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_UART0),
|
||||
};
|
||||
|
||||
static struct resource s5p_uart1_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_UART1, S5P_SZ_UART),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_UART1),
|
||||
};
|
||||
|
||||
static struct resource s5p_uart2_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_UART2, S5P_SZ_UART),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_UART2),
|
||||
};
|
||||
|
||||
static struct resource s5p_uart3_resource[] = {
|
||||
#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_UART3, S5P_SZ_UART),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_UART3),
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct resource s5p_uart4_resource[] = {
|
||||
#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_UART4, S5P_SZ_UART),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_UART4),
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct resource s5p_uart5_resource[] = {
|
||||
#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
|
||||
[0] = DEFINE_RES_MEM(S5P_PA_UART5, S5P_SZ_UART),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_UART5),
|
||||
#endif
|
||||
};
|
||||
|
||||
struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
|
||||
[0] = {
|
||||
.resources = s5p_uart0_resource,
|
||||
.nr_resources = ARRAY_SIZE(s5p_uart0_resource),
|
||||
},
|
||||
[1] = {
|
||||
.resources = s5p_uart1_resource,
|
||||
.nr_resources = ARRAY_SIZE(s5p_uart1_resource),
|
||||
},
|
||||
[2] = {
|
||||
.resources = s5p_uart2_resource,
|
||||
.nr_resources = ARRAY_SIZE(s5p_uart2_resource),
|
||||
},
|
||||
[3] = {
|
||||
.resources = s5p_uart3_resource,
|
||||
.nr_resources = ARRAY_SIZE(s5p_uart3_resource),
|
||||
},
|
||||
[4] = {
|
||||
.resources = s5p_uart4_resource,
|
||||
.nr_resources = ARRAY_SIZE(s5p_uart4_resource),
|
||||
},
|
||||
[5] = {
|
||||
.resources = s5p_uart5_resource,
|
||||
.nr_resources = ARRAY_SIZE(s5p_uart5_resource),
|
||||
},
|
||||
};
|
|
@ -1,221 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5P - IRQ EINT support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/irqchip/arm-vic.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <plat/regs-irqtype.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
static inline void s5p_irq_eint_mask(struct irq_data *data)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
|
||||
mask |= eint_irq_to_bit(data->irq);
|
||||
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
|
||||
}
|
||||
|
||||
static void s5p_irq_eint_unmask(struct irq_data *data)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
|
||||
mask &= ~(eint_irq_to_bit(data->irq));
|
||||
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
|
||||
}
|
||||
|
||||
static inline void s5p_irq_eint_ack(struct irq_data *data)
|
||||
{
|
||||
__raw_writel(eint_irq_to_bit(data->irq),
|
||||
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
|
||||
}
|
||||
|
||||
static void s5p_irq_eint_maskack(struct irq_data *data)
|
||||
{
|
||||
/* compiler should in-line these */
|
||||
s5p_irq_eint_mask(data);
|
||||
s5p_irq_eint_ack(data);
|
||||
}
|
||||
|
||||
static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
int offs = EINT_OFFSET(data->irq);
|
||||
int shift;
|
||||
u32 ctrl, mask;
|
||||
u32 newvalue = 0;
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
newvalue = S5P_IRQ_TYPE_EDGE_RISING;
|
||||
break;
|
||||
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
|
||||
break;
|
||||
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
|
||||
break;
|
||||
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
|
||||
break;
|
||||
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_ERR "No such irq type %d", type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
shift = (offs & 0x7) * 4;
|
||||
mask = 0x7 << shift;
|
||||
|
||||
ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
|
||||
ctrl &= ~mask;
|
||||
ctrl |= newvalue << shift;
|
||||
__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
|
||||
|
||||
if ((0 <= offs) && (offs < 8))
|
||||
s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
|
||||
|
||||
else if ((8 <= offs) && (offs < 16))
|
||||
s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
|
||||
|
||||
else if ((16 <= offs) && (offs < 24))
|
||||
s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
|
||||
|
||||
else if ((24 <= offs) && (offs < 32))
|
||||
s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
|
||||
|
||||
else
|
||||
printk(KERN_ERR "No such irq number %d", offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip s5p_irq_eint = {
|
||||
.name = "s5p-eint",
|
||||
.irq_mask = s5p_irq_eint_mask,
|
||||
.irq_unmask = s5p_irq_eint_unmask,
|
||||
.irq_mask_ack = s5p_irq_eint_maskack,
|
||||
.irq_ack = s5p_irq_eint_ack,
|
||||
.irq_set_type = s5p_irq_eint_set_type,
|
||||
#ifdef CONFIG_PM
|
||||
.irq_set_wake = s3c_irqext_wake,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* s5p_irq_demux_eint
|
||||
*
|
||||
* This function demuxes the IRQ from the group0 external interrupts,
|
||||
* from EINTs 16 to 31. It is designed to be inlined into the specific
|
||||
* handler s5p_irq_demux_eintX_Y.
|
||||
*
|
||||
* Each EINT pend/mask registers handle eight of them.
|
||||
*/
|
||||
static inline void s5p_irq_demux_eint(unsigned int start)
|
||||
{
|
||||
u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
|
||||
u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
|
||||
unsigned int irq;
|
||||
|
||||
status &= ~mask;
|
||||
status &= 0xff;
|
||||
|
||||
while (status) {
|
||||
irq = fls(status) - 1;
|
||||
generic_handle_irq(irq + start);
|
||||
status &= ~(1 << irq);
|
||||
}
|
||||
}
|
||||
|
||||
static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
s5p_irq_demux_eint(IRQ_EINT(16));
|
||||
s5p_irq_demux_eint(IRQ_EINT(24));
|
||||
}
|
||||
|
||||
static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(data);
|
||||
|
||||
s5p_irq_eint_mask(data);
|
||||
writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
|
||||
}
|
||||
|
||||
static void s5p_irq_vic_eint_unmask(struct irq_data *data)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(data);
|
||||
|
||||
s5p_irq_eint_unmask(data);
|
||||
writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
|
||||
}
|
||||
|
||||
static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
|
||||
{
|
||||
__raw_writel(eint_irq_to_bit(data->irq),
|
||||
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
|
||||
}
|
||||
|
||||
static void s5p_irq_vic_eint_maskack(struct irq_data *data)
|
||||
{
|
||||
s5p_irq_vic_eint_mask(data);
|
||||
s5p_irq_vic_eint_ack(data);
|
||||
}
|
||||
|
||||
static struct irq_chip s5p_irq_vic_eint = {
|
||||
.name = "s5p_vic_eint",
|
||||
.irq_mask = s5p_irq_vic_eint_mask,
|
||||
.irq_unmask = s5p_irq_vic_eint_unmask,
|
||||
.irq_mask_ack = s5p_irq_vic_eint_maskack,
|
||||
.irq_ack = s5p_irq_vic_eint_ack,
|
||||
.irq_set_type = s5p_irq_eint_set_type,
|
||||
#ifdef CONFIG_PM
|
||||
.irq_set_wake = s3c_irqext_wake,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init s5p_init_irq_eint(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (of_have_populated_dt())
|
||||
return -ENODEV;
|
||||
|
||||
for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
|
||||
irq_set_chip(irq, &s5p_irq_vic_eint);
|
||||
|
||||
for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
|
||||
irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(s5p_init_irq_eint);
|
|
@ -1,218 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* Author: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
|
||||
* Author: Marek Szyprowski <m.szyprowski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <plat/gpio-core.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
#define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
|
||||
|
||||
#define CON_OFFSET 0x700
|
||||
#define MASK_OFFSET 0x900
|
||||
#define PEND_OFFSET 0xA00
|
||||
#define REG_OFFSET(x) ((x) << 2)
|
||||
|
||||
struct s5p_gpioint_bank {
|
||||
struct list_head list;
|
||||
int start;
|
||||
int nr_groups;
|
||||
int irq;
|
||||
struct samsung_gpio_chip **chips;
|
||||
void (*handler)(unsigned int, struct irq_desc *);
|
||||
};
|
||||
|
||||
static LIST_HEAD(banks);
|
||||
|
||||
static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct irq_chip_type *ct = gc->chip_types;
|
||||
unsigned int shift = (d->irq - gc->irq_base) << 2;
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
type = S5P_IRQ_TYPE_EDGE_RISING;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
type = S5P_IRQ_TYPE_EDGE_FALLING;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
type = S5P_IRQ_TYPE_EDGE_BOTH;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
type = S5P_IRQ_TYPE_LEVEL_HIGH;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
type = S5P_IRQ_TYPE_LEVEL_LOW;
|
||||
break;
|
||||
case IRQ_TYPE_NONE:
|
||||
default:
|
||||
printk(KERN_WARNING "No irq type\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
gc->type_cache &= ~(0x7 << shift);
|
||||
gc->type_cache |= type << shift;
|
||||
writel(gc->type_cache, gc->reg_base + ct->regs.type);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
|
||||
int group, pend_offset, mask_offset;
|
||||
unsigned int pend, mask;
|
||||
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
for (group = 0; group < bank->nr_groups; group++) {
|
||||
struct samsung_gpio_chip *chip = bank->chips[group];
|
||||
if (!chip)
|
||||
continue;
|
||||
|
||||
pend_offset = REG_OFFSET(group);
|
||||
pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
|
||||
if (!pend)
|
||||
continue;
|
||||
|
||||
mask_offset = REG_OFFSET(group);
|
||||
mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
|
||||
pend &= ~mask;
|
||||
|
||||
while (pend) {
|
||||
int offset = fls(pend) - 1;
|
||||
int real_irq = chip->irq_base + offset;
|
||||
generic_handle_irq(real_irq);
|
||||
pend &= ~BIT(offset);
|
||||
}
|
||||
}
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
|
||||
{
|
||||
static int used_gpioint_groups = 0;
|
||||
int group = chip->group;
|
||||
struct s5p_gpioint_bank *b, *bank = NULL;
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_chip_type *ct;
|
||||
|
||||
if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
|
||||
return -ENOMEM;
|
||||
|
||||
list_for_each_entry(b, &banks, list) {
|
||||
if (group >= b->start && group < b->start + b->nr_groups) {
|
||||
bank = b;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!bank)
|
||||
return -EINVAL;
|
||||
|
||||
if (!bank->handler) {
|
||||
bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) *
|
||||
bank->nr_groups, GFP_KERNEL);
|
||||
if (!bank->chips)
|
||||
return -ENOMEM;
|
||||
|
||||
irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
|
||||
irq_set_handler_data(bank->irq, bank);
|
||||
bank->handler = s5p_gpioint_handler;
|
||||
printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
|
||||
bank->irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* chained GPIO irq has been successfully registered, allocate new gpio
|
||||
* int group and assign irq nubmers
|
||||
*/
|
||||
chip->irq_base = S5P_GPIOINT_BASE +
|
||||
used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
|
||||
used_gpioint_groups++;
|
||||
|
||||
bank->chips[group - bank->start] = chip;
|
||||
|
||||
gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
|
||||
GPIO_BASE(chip),
|
||||
handle_level_irq);
|
||||
if (!gc)
|
||||
return -ENOMEM;
|
||||
ct = gc->chip_types;
|
||||
ct->chip.irq_ack = irq_gc_ack_set_bit;
|
||||
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
||||
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||
ct->chip.irq_set_type = s5p_gpioint_set_type,
|
||||
ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
|
||||
ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
|
||||
ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
|
||||
irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
|
||||
IRQ_GC_INIT_MASK_CACHE,
|
||||
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init s5p_register_gpio_interrupt(int pin)
|
||||
{
|
||||
struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin);
|
||||
int offset, group;
|
||||
int ret;
|
||||
|
||||
if (!my_chip)
|
||||
return -EINVAL;
|
||||
|
||||
offset = pin - my_chip->chip.base;
|
||||
group = my_chip->group;
|
||||
|
||||
/* check if the group has been already registered */
|
||||
if (my_chip->irq_base)
|
||||
goto success;
|
||||
|
||||
/* register gpio group */
|
||||
ret = s5p_gpioint_add(my_chip);
|
||||
if (ret == 0) {
|
||||
my_chip->chip.to_irq = samsung_gpiolib_to_irq;
|
||||
printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
|
||||
group);
|
||||
goto success;
|
||||
}
|
||||
return ret;
|
||||
success:
|
||||
my_chip->bitmap_gpio_int |= BIT(offset);
|
||||
|
||||
return my_chip->irq_base + offset;
|
||||
}
|
||||
|
||||
int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
|
||||
{
|
||||
struct s5p_gpioint_bank *bank;
|
||||
|
||||
bank = kzalloc(sizeof(*bank), GFP_KERNEL);
|
||||
if (!bank)
|
||||
return -ENOMEM;
|
||||
|
||||
bank->start = start;
|
||||
bank->nr_groups = nr_groups;
|
||||
bank->irq = chain_irq;
|
||||
|
||||
list_add_tail(&bank->list, &banks);
|
||||
return 0;
|
||||
}
|
|
@ -1,92 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Based on arch/arm/plat-s3c24xx/irq-pm.c,
|
||||
* Copyright (c) 2003,2004 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/irqs.h>
|
||||
#include <plat/pm.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-irq.h>
|
||||
|
||||
/* state for IRQs over sleep */
|
||||
|
||||
/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
|
||||
* as wakeup sources
|
||||
*
|
||||
* set bit to 1 in allow bitfield to enable the wakeup settings on it
|
||||
*/
|
||||
|
||||
unsigned long s3c_irqwake_intallow = 0x00000006L;
|
||||
unsigned long s3c_irqwake_eintallow = 0xffffffffL;
|
||||
|
||||
int s3c_irq_wake(struct irq_data *data, unsigned int state)
|
||||
{
|
||||
unsigned long irqbit;
|
||||
unsigned int irq_rtc_tic, irq_rtc_alarm;
|
||||
|
||||
irq_rtc_tic = IRQ_RTC_TIC;
|
||||
irq_rtc_alarm = IRQ_RTC_ALARM;
|
||||
|
||||
if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
|
||||
irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
|
||||
|
||||
if (!state)
|
||||
s3c_irqwake_intmask |= irqbit;
|
||||
else
|
||||
s3c_irqwake_intmask &= ~irqbit;
|
||||
} else {
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sleep_save eint_save[] = {
|
||||
SAVE_ITEM(S5P_EINT_CON(0)),
|
||||
SAVE_ITEM(S5P_EINT_CON(1)),
|
||||
SAVE_ITEM(S5P_EINT_CON(2)),
|
||||
SAVE_ITEM(S5P_EINT_CON(3)),
|
||||
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(0)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(1)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(2)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(3)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(4)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(5)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(6)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(7)),
|
||||
|
||||
SAVE_ITEM(S5P_EINT_MASK(0)),
|
||||
SAVE_ITEM(S5P_EINT_MASK(1)),
|
||||
SAVE_ITEM(S5P_EINT_MASK(2)),
|
||||
SAVE_ITEM(S5P_EINT_MASK(3)),
|
||||
};
|
||||
|
||||
int s3c24xx_irq_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void s3c24xx_irq_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
|
||||
}
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5P - Interrupt handling
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-vic.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
void __init s5p_init_irq(u32 *vic, u32 num_vic)
|
||||
{
|
||||
#ifdef CONFIG_ARM_VIC
|
||||
int irq;
|
||||
|
||||
/* initialize the VICs */
|
||||
for (irq = 0; irq < num_vic; irq++)
|
||||
vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
|
||||
#endif
|
||||
}
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5P Power Manager (Suspend-To-RAM) support
|
||||
*
|
||||
* Based on arch/arm/plat-s3c24xx/pm.c
|
||||
* Copyright (c) 2004,2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/suspend.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#define PFX "s5p pm: "
|
||||
|
||||
/* s3c_pm_configure_extint
|
||||
*
|
||||
* configure all external interrupt pins
|
||||
*/
|
||||
|
||||
void s3c_pm_configure_extint(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
void s3c_pm_restore_core(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
void s3c_pm_save_core(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Common S5P Sleep Code
|
||||
* Based on S3C64XX sleep code by:
|
||||
* Ben Dooks, (c) 2008 Simtec Electronics
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
.data
|
||||
.align
|
||||
|
||||
/*
|
||||
* sleep magic, to allow the bootloader to check for an valid
|
||||
* image to resume to. Must be the first word before the
|
||||
* s3c_cpu_resume entry.
|
||||
*/
|
||||
|
||||
.word 0x2bedf00d
|
||||
|
||||
/*
|
||||
* s3c_cpu_resume
|
||||
*
|
||||
* resume code entry for bootloader to call
|
||||
*/
|
||||
|
||||
ENTRY(s3c_cpu_resume)
|
||||
b cpu_resume
|
||||
ENDPROC(s3c_cpu_resume)
|
Loading…
Reference in a new issue