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[ALSA] hdsp - Add DDS register support for RME9632 rev >= 152
Add DDS register support for RME9632 rev >= 152. This register sets the sample rate for these cards and is required in addition to the standard control register. It corresponds to a quartz divisor. Signed-off-by: Remy Bruno <remy.bruno@trinnov.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
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1 changed files with 36 additions and 0 deletions
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@ -80,6 +80,7 @@ MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
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/* Write registers. These are defined as byte-offsets from the iobase value.
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*/
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#define HDSP_resetPointer 0
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#define HDSP_freqReg 0
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#define HDSP_outputBufferAddress 32
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#define HDSP_inputBufferAddress 36
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#define HDSP_controlRegister 64
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@ -469,6 +470,7 @@ struct hdsp {
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struct pci_dev *pci;
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struct snd_kcontrol *spdif_ctl;
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unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
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unsigned int dds_value; /* last value written to freq register */
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};
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/* These tables map the ALSA channels 1..N to the channels that we
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@ -940,6 +942,11 @@ static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
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static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
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{
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hdsp_write (hdsp, HDSP_resetPointer, 0);
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if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
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/* HDSP_resetPointer = HDSP_freqReg, which is strange and
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* requires (?) to write again DDS value after a reset pointer
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* (at least, it works like this) */
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hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
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}
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static void hdsp_start_audio(struct hdsp *s)
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@ -984,6 +991,30 @@ static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
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return 0;
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}
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static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
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{
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u64 n;
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u32 r;
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if (rate >= 112000)
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rate /= 4;
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else if (rate >= 56000)
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rate /= 2;
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/* RME says n = 104857600000000, but in the windows MADI driver, I see:
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// return 104857600000000 / rate; // 100 MHz
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return 110100480000000 / rate; // 105 MHz
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*/
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n = 104857600000000ULL; /* = 2^20 * 10^8 */
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div64_32(&n, rate, &r);
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/* n should be less than 2^32 for being written to FREQ register */
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snd_assert((n >> 32) == 0);
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/* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
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value to write it after a reset */
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hdsp->dds_value = n;
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hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
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}
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static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
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{
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int reject_if_open = 0;
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@ -1092,6 +1123,10 @@ static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
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hdsp->control_register |= rate_bits;
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hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
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/* For HDSP9632 rev 152, need to set DDS value in FREQ register */
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if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
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hdsp_set_dds_value(hdsp, rate);
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if (rate >= 128000) {
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hdsp->channel_map = channel_map_H9632_qs;
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} else if (rate > 48000) {
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@ -4945,6 +4980,7 @@ static int __devinit snd_hdsp_create(struct snd_card *card,
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hdsp->irq = pci->irq;
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hdsp->precise_ptr = 0;
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hdsp->use_midi_tasklet = 1;
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hdsp->dds_value = 0;
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if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
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return err;
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