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ARC: TLB flush Handling
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
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3 changed files with 356 additions and 0 deletions
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@ -21,6 +21,23 @@
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#ifndef __ASSEMBLY__
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#define tlb_flush(tlb) local_flush_tlb_mm((tlb)->mm)
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/*
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* This pair is called at time of munmap/exit to flush cache and TLB entries
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* for mappings being torn down.
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* 1) cache-flush part -implemented via tlb_start_vma( ) can be NOP (for now)
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* as we don't support aliasing configs in our VIPT D$.
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* 2) tlb-flush part - implemted via tlb_end_vma( ) can be NOP as well-
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* albiet for difft reasons - its better handled by moving to new ASID
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*
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* Note, read http://lkml.org/lkml/2004/1/15/6
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*/
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#define tlb_start_vma(tlb, vma)
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#define tlb_end_vma(tlb, vma)
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#define __tlb_remove_tlb_entry(tlb, ptep, address)
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#include <linux/pagemap.h>
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#include <asm-generic/tlb.h>
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28
arch/arc/include/asm/tlbflush.h
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28
arch/arc/include/asm/tlbflush.h
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@ -0,0 +1,28 @@
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARC_TLBFLUSH__
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#define __ASM_ARC_TLBFLUSH__
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#include <linux/mm.h>
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void local_flush_tlb_all(void);
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void local_flush_tlb_mm(struct mm_struct *mm);
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end);
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void local_flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end);
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/* XXX: Revisit for SMP */
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#define flush_tlb_range(vma, s, e) local_flush_tlb_range(vma, s, e)
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#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
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#define flush_tlb_kernel_range(s, e) local_flush_tlb_kernel_range(s, e)
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#define flush_tlb_all() local_flush_tlb_all()
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#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
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#endif
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@ -6,13 +6,97 @@
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: Aug 2011
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* -Reintroduce duplicate PD fixup - some customer chips still have the issue
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*
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* vineetg: May 2011
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* -No need to flush_cache_page( ) for each call to update_mmu_cache()
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* some of the LMBench tests improved amazingly
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* = page-fault thrice as fast (75 usec to 28 usec)
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* = mmap twice as fast (9.6 msec to 4.6 msec),
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* = fork (5.3 msec to 3.7 msec)
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*
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* vineetg: April 2011 :
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* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
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* helps avoid a shift when preparing PD0 from PTE
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*
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* vineetg: April 2011 : Preparing for MMU V3
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* -MMU v2/v3 BCRs decoded differently
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* -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
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* -tlb_entry_erase( ) can be void
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* -local_flush_tlb_range( ):
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* = need not "ceil" @end
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* = walks MMU only if range spans < 32 entries, as opposed to 256
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*
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* Vineetg: Sept 10th 2008
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* -Changes related to MMU v2 (Rel 4.8)
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*
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* Vineetg: Aug 29th 2008
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* -In TLB Flush operations (Metal Fix MMU) there is a explict command to
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* flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
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* it fails. Thus need to load it with ANY valid value before invoking
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* TLBIVUTLB cmd
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*
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* Vineetg: Aug 21th 2008:
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* -Reduced the duration of IRQ lockouts in TLB Flush routines
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* -Multiple copies of TLB erase code seperated into a "single" function
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* -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
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* in interrupt-safe region.
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*
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* Vineetg: April 23rd Bug #93131
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* Problem: tlb_flush_kernel_range() doesnt do anything if the range to
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* flush is more than the size of TLB itself.
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*
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* Rahul Trivedi : Codito Technologies 2004
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*/
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#include <linux/module.h>
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#include <asm/arcregs.h>
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#include <asm/setup.h>
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#include <asm/mmu_context.h>
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#include <asm/tlb.h>
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/* Need for ARC MMU v2
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*
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* ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
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* For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
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* map into same set, there would be contention for the 2 ways causing severe
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* Thrashing.
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*
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* Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
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* much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
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* Given this, the thrasing problem should never happen because once the 3
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* J-TLB entries are created (even though 3rd will knock out one of the prev
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* two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
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*
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* Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
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* This is a simple design for keeping them in sync. So what do we do?
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* The solution which James came up was pretty neat. It utilised the assoc
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* of uTLBs by not invalidating always but only when absolutely necessary.
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*
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* - Existing TLB commands work as before
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* - New command (TLBWriteNI) for TLB write without clearing uTLBs
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* - New command (TLBIVUTLB) to invalidate uTLBs.
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*
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* The uTLBs need only be invalidated when pages are being removed from the
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* OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
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* as a result of a miss, the removed entry is still allowed to exist in the
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* uTLBs as it is still valid and present in the OS page table. This allows the
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* full associativity of the uTLBs to hide the limited associativity of the main
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* TLB.
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*
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* During a miss handler, the new "TLBWriteNI" command is used to load
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* entries without clearing the uTLBs.
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*
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* When the OS page table is updated, TLB entries that may be associated with a
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* removed page are removed (flushed) from the TLB using TLBWrite. In this
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* circumstance, the uTLBs must also be cleared. This is done by using the
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* existing TLBWrite command. An explicit IVUTLB is also required for those
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* corner cases when TLBWrite was not executed at all because the corresp
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* J-TLB entry got evicted/replaced.
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*/
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/* A copy of the ASID from the PID reg is kept in asid_cache */
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int asid_cache = FIRST_ASID;
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*/
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struct mm_struct *asid_mm_map[NUM_ASID + 1];
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/*
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* Utility Routine to erase a J-TLB entry
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* The procedure is to look it up in the MMU. If found, ERASE it by
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* issuing a TlbWrite CMD with PD0 = PD1 = 0
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*/
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static void __tlb_entry_erase(void)
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{
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write_aux_reg(ARC_REG_TLBPD1, 0);
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write_aux_reg(ARC_REG_TLBPD0, 0);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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static void tlb_entry_erase(unsigned int vaddr_n_asid)
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{
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unsigned int idx;
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/* Locate the TLB entry for this vaddr + ASID */
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write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
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idx = read_aux_reg(ARC_REG_TLBINDEX);
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/* No error means entry found, zero it out */
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if (likely(!(idx & TLB_LKUP_ERR))) {
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__tlb_entry_erase();
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} else { /* Some sort of Error */
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/* Duplicate entry error */
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if (idx & 0x1) {
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/* TODO we need to handle this case too */
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pr_emerg("unhandled Duplicate flush for %x\n",
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vaddr_n_asid);
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}
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/* else entry not found so nothing to do */
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}
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}
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/****************************************************************************
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* ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
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*
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* New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
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*
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* utlb_invalidate ( )
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* -For v2 MMU calls Flush uTLB Cmd
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* -For v1 MMU does nothing (except for Metal Fix v1 MMU)
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* This is because in v1 TLBWrite itself invalidate uTLBs
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***************************************************************************/
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static void utlb_invalidate(void)
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{
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#if (CONFIG_ARC_MMU_VER >= 2)
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#if (CONFIG_ARC_MMU_VER < 3)
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/* MMU v2 introduced the uTLB Flush command.
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* There was however an obscure hardware bug, where uTLB flush would
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* fail when a prior probe for J-TLB (both totally unrelated) would
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* return lkup err - because the entry didnt exist in MMU.
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* The Workround was to set Index reg with some valid value, prior to
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* flush. This was fixed in MMU v3 hence not needed any more
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*/
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unsigned int idx;
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/* make sure INDEX Reg is valid */
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idx = read_aux_reg(ARC_REG_TLBINDEX);
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/* If not write some dummy val */
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if (unlikely(idx & TLB_LKUP_ERR))
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write_aux_reg(ARC_REG_TLBINDEX, 0xa);
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#endif
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
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#endif
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}
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/*
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* Un-conditionally (without lookup) erase the entire MMU contents
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*/
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noinline void local_flush_tlb_all(void)
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{
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unsigned long flags;
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unsigned int entry;
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
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local_irq_save(flags);
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/* Load PD0 and PD1 with template for a Blank Entry */
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write_aux_reg(ARC_REG_TLBPD1, 0);
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write_aux_reg(ARC_REG_TLBPD0, 0);
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for (entry = 0; entry < mmu->num_tlb; entry++) {
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/* write this entry to the TLB */
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write_aux_reg(ARC_REG_TLBINDEX, entry);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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utlb_invalidate();
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local_irq_restore(flags);
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}
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/*
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* Flush the entrie MM for userland. The fastest way is to move to Next ASID
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*/
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noinline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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/*
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* Small optimisation courtesy IA64
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* flush_mm called during fork,exit,munmap etc, multiple times as well.
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* Only for fork( ) do we need to move parent to a new MMU ctxt,
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* all other cases are NOPs, hence this check.
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*/
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if (atomic_read(&mm->mm_users) == 0)
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return;
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/*
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* Workaround for Android weirdism:
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* A binder VMA could end up in a task such that vma->mm != tsk->mm
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* old code would cause h/w - s/w ASID to get out of sync
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*/
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if (current->mm != mm)
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destroy_context(mm);
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else
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get_new_mmu_context(mm);
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}
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/*
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* Flush a Range of TLB entries for userland.
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* @start is inclusive, while @end is exclusive
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* Difference between this and Kernel Range Flush is
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* -Here the fastest way (if range is too large) is to move to next ASID
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* without doing any explicit Shootdown
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* -In case of kernel Flush, entry has to be shot down explictly
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*/
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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unsigned long flags;
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unsigned int asid;
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/* If range @start to @end is more than 32 TLB entries deep,
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* its better to move to a new ASID rather than searching for
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* individual entries and then shooting them down
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*
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* The calc above is rough, doesn't account for unaligned parts,
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* since this is heuristics based anyways
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*/
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if (unlikely((end - start) >= PAGE_SIZE * 32)) {
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local_flush_tlb_mm(vma->vm_mm);
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return;
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}
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/*
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* @start moved to page start: this alone suffices for checking
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* loop end condition below, w/o need for aligning @end to end
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* e.g. 2000 to 4001 will anyhow loop twice
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*/
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start &= PAGE_MASK;
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local_irq_save(flags);
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asid = vma->vm_mm->context.asid;
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if (asid != NO_ASID) {
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while (start < end) {
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tlb_entry_erase(start | (asid & 0xff));
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start += PAGE_SIZE;
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}
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}
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utlb_invalidate();
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local_irq_restore(flags);
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}
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/* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
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* @start, @end interpreted as kvaddr
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* Interestingly, shared TLB entries can also be flushed using just
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* @start,@end alone (interpreted as user vaddr), although technically SASID
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* is also needed. However our smart TLbProbe lookup takes care of that.
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*/
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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/* exactly same as above, except for TLB entry not taking ASID */
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if (unlikely((end - start) >= PAGE_SIZE * 32)) {
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local_flush_tlb_all();
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return;
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}
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start &= PAGE_MASK;
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local_irq_save(flags);
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while (start < end) {
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tlb_entry_erase(start);
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start += PAGE_SIZE;
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}
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utlb_invalidate();
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local_irq_restore(flags);
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}
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/*
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* Delete TLB entry in MMU for a given page (??? address)
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* NOTE One TLB entry contains translation for single PAGE
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*/
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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unsigned long flags;
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/* Note that it is critical that interrupts are DISABLED between
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* checking the ASID and using it flush the TLB entry
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*/
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local_irq_save(flags);
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if (vma->vm_mm->context.asid != NO_ASID) {
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tlb_entry_erase((page & PAGE_MASK) |
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(vma->vm_mm->context.asid & 0xff));
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utlb_invalidate();
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}
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local_irq_restore(flags);
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}
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/*
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* Routine to create a TLB entry
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